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Travelled to:
3 × Germany
3 × USA
6 × France
Collaborated with:
A.Sreedhar O.Khan I.Pomeranz S.M.Reddy A.Vijayakumar M.Buttrick K.Nagaraj K.P.Ganeshpure C.Tirumurti Y.Chang U.Ghoshal A.Pan A.Sanyal A.Rastogi W.Chen B.Grundmann R.Galivanche S.Sur-Kolay S.T.Zachariah J.Liou K.Cheng A.Krstic
Talks about:
design (6) circuit (5) model (5) test (5) analysi (4) fault (4) base (4) process (3) variat (3) cmos (3)

Person: Sandip Kundu

DBLP DBLP: Kundu:Sandip

Contributed to:

DATE 20152015
DATE 20112011
DATE 20092009
DATE 20082008
DAC 20072007
DATE 20072007
DATE 20062006
DATE v2 20042004
DATE 20032003
DAC 20022002
DAC 20012001
ED&TC 19971997

Wrote 21 papers:

DATE-2015-VijayakumarK #design #modelling #novel
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics (AV, SK), pp. 653–658.
DATE-2011-ButtrickK #3d #network #on the #testing #using
On testing prebond dies with incomplete clock networks in a 3D IC using DLLs (MB, SK), pp. 1418–1423.
DATE-2011-KunduS #design #modelling #process
Modeling manufacturing process variation for design and test (SK, AS), pp. 1147–1152.
DATE-2011-SreedharK #design #identification #on the #process
On design of test structures for lithographic process corner identification (AS, SK), pp. 800–805.
DATE-2011-SreedharK11a #security
Physically unclonable functions for embeded security based on lithographic variation (AS, SK), pp. 1632–1637.
DATE-2009-KhanK #adaptation #architecture #self
A self-adaptive system architecture to address transistor aging (OK, SK), pp. 81–86.
DATE-2009-KhanK09a #architecture #co-evolution #design #hardware #multi
Hardware/software co-design architecture for thermal management of chip multiprocessors (OK, SK), pp. 952–957.
DATE-2009-NagarajK #case study #process
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (KN, SK), pp. 292–295.
DATE-2009-PanKK #multi #reliability
Improving yield and reliability of chip multiprocessors (AP, OK, SK), pp. 490–495.
DATE-2009-SreedharK #analysis #on the
On linewidth-based yield analysis for nanometer lithography (AS, SK), pp. 381–386.
DATE-2008-SreedharSK #fault #modelling #on the #testing
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits (AS, AS, SK), pp. 616–621.
DAC-2007-RastogiCK #on the
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method (AR, WC, SK), pp. 712–715.
DATE-2007-GaneshpureK #automation #fault #generative #interactive #multi
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults (KPG, SK), pp. 540–545.
DATE-2006-Kundu #analysis #design
A design for failure analysis (DFFA) technique to ensure incorruptible signatures (SK), pp. 309–310.
DATE-v2-2004-TirumurtiKSC #approach #modelling #power management
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit (CT, SK, SSK, YSC), pp. 1078–1083.
DATE-2003-GrundmannGK #challenge #design #framework #platform
Circuit and Platform Design Challenges in Technologies beyond 90nm (BG, RG, SK), pp. 10044–10049.
DATE-2003-PomeranzRK #detection #fault #on the
On the Characterization of Hard-to-Detect Bridging Faults (IP, SMR, SK), pp. 11012–11019.
DATE-2003-ZachariahCKT #fault #modelling #on the
On Modeling Cross-Talk Faults (STZ, YSC, SK, CT), pp. 10490–10495.
DAC-2002-PomeranzKR #on the
On output response compression in the presence of unknown output values (IP, SK, SMR), pp. 255–258.
DAC-2001-LiouCKK #analysis #performance #probability #statistics
Fast Statistical Timing Analysis By Probabilistic Event Propagation (JJL, KTC, SK, AK), pp. 661–666.
EDTC-1997-KunduG #analysis
Inductance analysis of on-chip interconnects [deep submicron CMOS] (SK, UG), pp. 252–255.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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