BibSLEIGH — Proceedings of the 13th Conference on Design, Automation and Test in Europe

Proceedings of the 13th Conference on Design, Automation and Test in Europe
DATE, 2009.

SYS

@proceedings{DATE-2009,
	address       = "Nice, France",
	publisher     = "{IEEE}",
	title         = "{Proceedings of the 13th Conference on Design, Automation and Test in Europe}",
	year          = 2009,
}

Contents (310 items)

DATE-2009-Muller #design #question: Has anything changed in electronic design since 1983? (MM), p. 1.
DATE-2009-Sifakis #challenge #design #embedded: Embedded systems design — Scientific challenges and work directions (JS), p. 2.
DATE-2009-GuXZ #multi #power management: A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip (HG, JX, WZ), pp. 3–8.
DATE-2009-SeiculescuMBM #3d #network #synthesis: SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips (CS, SM, LB, GDM), pp. 9–14.
DATE-2009-ChouM #design: User-centric design space exploration for heterogeneous Network-on-Chip platforms (CLC, RM), pp. 15–20.
DATE-2009-FickDCBSB #algorithm #fault tolerance: A highly resilient routing algorithm for fault-tolerant NoCs (DF, AD, GKC, VB, DS, DB), pp. 21–26.
DATE-2009-WhittySEP #algorithm #architecture #configuration management: Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture (SW, HS, RE, WPR), pp. 27–32.
DATE-2009-YiHZEA #architecture #manycore #scheduling: An ILP formulation for task mapping and scheduling on multi-core architectures (YY, WH, XZ, ATE, TA), pp. 33–38.
DATE-2009-GaoKMAMK #energy #physics: DPR in high energy physics (WG, AK, RM, NA, NM, UK), pp. 39–44.
DATE-2009-AlimohammadFC #algorithm #architecture #development #flexibility #verification: A flexible layered architecture for accurate digital baseband algorithm development and verification (AA, SFF, BFC), pp. 45–50.
DATE-2009-HuangYX #scheduling: Lifetime reliability-aware task allocation and scheduling for MPSoC platforms (LH, FY, QX), pp. 51–56.
DATE-2009-SamiiCEP #distributed #embedded #scheduling #synthesis: Integrated scheduling and synthesis of control applications on distributed embedded systems (SS, AC, PE, ZP), pp. 57–62.
DATE-2009-YangO #adaptation #towards: Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude (CY, AO), pp. 63–68.
DATE-2009-YangH #parallel #pipes and filters #scheduling: Pipelined data parallel task mapping/scheduling technique for MPSoC (HY, SH), pp. 69–74.
DATE-2009-WuM #logic #order #performance: Joint logic restructuring and pin reordering against NBTI-induced performance degradation (KCW, DM), pp. 75–80.
DATE-2009-KhanK #adaptation #architecture #self: A self-adaptive system architecture to address transistor aging (OK, SK), pp. 81–86.
DATE-2009-ChoudhuryM #fault #logic: Masking timing errors on speed-paths in logic circuits (MRC, KM), pp. 87–92.
DATE-2009-MendlerHT #algebra #interface: WCRT algebra and interfaces for esterel-style synchronous processing (MM, RvH, CT), pp. 93–98.
DATE-2009-StoimenovPT #realtime #reliability #scheduling: Reliable mode changes in real-time systems with fixed priority or EDF scheduling (NS, SP, LT), pp. 99–104.
DATE-2009-PollexKAS #bound #worst-case: Improved worst-case response-time calculations by upper-bound conditions (VP, SK, KA, FS), pp. 105–110.
DATE-2009-PlishkerSB #approach #data flow #scheduling: A generalized scheduling approach for dynamic dataflow applications (WP, NS, SSB), pp. 111–116.
DATE-2009-Gomez-PradoRCGB #data flow #graph #hardware #implementation #optimisation: Optimizing data flow graphs to minimize hardware implementation (DGP, QR, MJC, JG, EB), pp. 117–122.
DATE-2009-SinhaRBS #design #multi #protocol #using: Multi-clock Soc design using protocol conversion (RS, PSR, SB, ZS), pp. 123–128.
DATE-2009-AvnitS #approach #design #formal method #protocol: A formal approach to design space exploration of protocol converters (KA, AS), pp. 129–134.
DATE-2009-KeinertDHHT #algorithm #image #modelling #multi #optimisation #synthesis: Model-based synthesis and optimization of static multi-rate image processing algorithms (JK, HD, FH, CH, JT), pp. 135–140.
DATE-2009-MishraAZ #adaptation: Variation resilient adaptive controller for subthreshold circuits (BM, BMAH, MZ), pp. 142–147.
DATE-2009-BildBD #performance #using: Minimization of NBTI performance degradation using internal node control (DRB, GEB, RPD), pp. 148–153.
DATE-2009-SathanurPBMM #clustering #design #variability: Physically clustered forward body biasing for variability compensation in nanometer CMOS design (AVS, AP, LB, GDM, EM), pp. 154–159.
DATE-2009-GuptaRHWB #approach: An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
DATE-2009-AfratisGSMCPP #database #design #implementation: Design and implementation of a database filter for BLAST acceleration (PA, CG, ES, GGM, GC, IP, DNP), pp. 166–171.
DATE-2009-SioziosPS #3d #architecture: A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs (KS, VFP, DS), pp. 172–177.
DATE-2009-SanderGRBM #communication: Priority-based packet communication on a bus-shaped structure for FPGA-systems (OS, BG, CR, JB, KDMG), pp. 178–183.
DATE-2009-AhmedERCST #performance #pipes and filters #programmable #reduction: Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (SZA, JE, LR, JBC, GS, LT), pp. 184–189.
DATE-2009-BombieriFPHL #functional #verification: Functional qualification of TLM verification (NB, FF, GP, MH, FL), pp. 190–195.
DATE-2009-KoelblJJP #equivalence: Solver technology for system-level to RTL equivalence checking (AK, RJ, HJ, CP), pp. 196–201.
DATE-2009-GoossensVN #debugging: A high-level debug environment for communication-centric debug (KG, BV, ABN), pp. 202–207.
DATE-2009-VishnoiPB #debugging: Cache aware compression for processor debug support (AV, PRP, MB), pp. 208–213.
DATE-2009-GriessnigMSW #fault #novel #testing: Fault insertion testing of a novel CPLD-based fail-safe system (GG, RM, CS, RW), pp. 214–219.
DATE-2009-JiangHX #3d #architecture #design #optimisation: Test architecture design and optimization for three-dimensional SoCs (LJ, LH, QX), pp. 220–225.
DATE-2009-VidalLGSD #approach #co-evolution #code generation #design #embedded #modelling #uml: A co-design approach for embedded system modeling and code generation with UML and MARTE (JV, FdL, GG, PS, JPD), pp. 226–231.
DATE-2009-HaoX #component #design #hardware #interface: Componentizing hardware/software interface design (KH, FX), pp. 232–237.
DATE-2009-SchattkowskyXM #uml: A UML frontend for IP-XACT-based IP management (TS, TX, WM), pp. 238–243.
DATE-2009-ArpinenKSHH #automation #integration #modelling #uml: Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA (TA, TK, ES, TDH, MH), pp. 244–249.
DATE-2009-HanssonSG #composition #named #network #predict: Aelite: A flit-synchronous Network on Chip with composable and predictable services (AH, MS, KG), pp. 250–255.
DATE-2009-FaruqueEH #adaptation #communication #configuration management #runtime: Configurable links for runtime adaptive on-chip communication (MAAF, TE, JH), pp. 256–261.
DATE-2009-LoiAB #configuration management #interface #network #synthesis: Synthesis of low-overhead configurable source routing tables for network interfaces (IL, FA, LB), pp. 262–267.
DATE-2009-Jara-BerrocalG #architecture #communication #composition #configuration management #named #parametricity #scalability: SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems (AJB, AGR), pp. 268–273.
DATE-2009-GrabBCCFLS #layout #synthesis: Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DATE-2009-WangM #using: An accurate interconnect thermal model using equivalent transmission line circuit (BW, PM), pp. 280–283.
DATE-2009-KirchnerBG #simulation #using: Analogue mixed signal simulation using spice and SystemC (TK, NB, CG), pp. 284–287.
DATE-2009-AraniHPCYPTC #3d #reliability: Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.
DATE-2009-NagarajK #case study #process: A study on placement of post silicon clock tuning buffers for mitigating impact of process variation (KN, SK), pp. 292–295.
DATE-2009-ChakrabortyGRP #analysis #optimisation: Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
DATE-2009-FlynnGG #configuration management: Bitstream relocation with local clock domains for partially reconfigurable FPGAs (AF, AGR, ADG), pp. 300–303.
DATE-2009-PengC #parallel #simulation: Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.
DATE-2009-ChenL #design: Performance-driven dual-rail insertion for chip-level pre-fabricated design (FWC, YYL), pp. 308–311.
DATE-2009-TrautmannMBDUDPC #case study #framework #simulation: Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning (MT, SM, BB, JD, EU, AD, LVdP, FC), pp. 312–315.
DATE-2009-MollCRB #modelling #performance #protocol #using: Fast and accurate protocol specific bus modeling using TLM 2.0 (HWMvM, HC, VR, MB), pp. 316–319.
DATE-2009-GlassLHT #design #embedded: Incorporating graceful degradation into embedded system design (MG, ML, CH, JT), pp. 320–323.
DATE-2009-LinW #using: Rewiring using IRredundancy Removal and Addition (CCL, CYW), pp. 324–327.
DATE-2009-0002CWCXY #optimisation: Gate replacement techniques for simultaneous leakage and aging optimization (YW, XC, WW, YC, YX, HY), pp. 328–333.
DATE-2009-BolzaniCMMP #concurrent #design #industrial #power management: Enabling concurrent clock and power gating in an industrial design flow (LMVB, AC, AM, EM, MP), pp. 334–339.
DATE-2009-KhajehGDKEKA #design #memory management #named #reliability: TRAM: A tool for Temperature and Reliability Aware Memory Design (AK, AG, ND, FJK, AME, KSK, MSA), pp. 340–345.
DATE-2009-CasteresR #architecture #integration #modelling #realtime #trade-off: Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs (JC, TR), pp. 346–351.
DATE-2009-ReordaVMR #embedded #low cost: A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-2009-GhasemzadehJSJ #communication #network: Communication minimization for in-network processing in body sensor networks: A buffer assignment technique (HG, NJ, MS, RJ), pp. 358–363.
DATE-2009-LarcherBGIBG #configuration management #standard: A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard (LL, RB, MG, JI, MB, AG), pp. 364–368.
DATE-2009-Diaz-MadridNHDR #pipes and filters #reduction: Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing (JÁDM, HN, HH, GDA, RRM), pp. 369–373.
DATE-2009-RedaN #metric #modelling #novel #parametricity #process: Analyzing the impact of process variations on parametric measurements: Novel models and applications (SR, SRN), pp. 375–380.
DATE-2009-SreedharK #analysis #on the: On linewidth-based yield analysis for nanometer lithography (AS, SK), pp. 381–386.
DATE-2009-ChandraA #reliability #scalability: Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.
DATE-2009-WuCK #design: A file-system-aware FTL design for flash-memory storage systems (PLW, YHC, TWK), pp. 393–398.
DATE-2009-MylavarapuCSLG #file system #named: FSAF: File system aware flash translation layer for NAND Flash Memories (SKM, SC, AS, JL, TG), pp. 399–404.
DATE-2009-ChuHCK #reliability: A set-based mapping strategy for flash-memory reliability enhancement (YSC, JWH, YHC, TWK), pp. 405–410.
DATE-2009-CongG #energy #multi #performance #scheduling: Energy efficient multiprocessor task scheduling under input-dependent variation (JC, KG), pp. 411–416.
DATE-2009-KimYK #online #runtime #scalability: Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling (JK, SY, CMK), pp. 417–422.
DATE-2009-KahngLPS #design #performance: ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (ABK, BL, LSP, KS), pp. 423–428.
DATE-2009-Anghel #concurrent #development #topic: HOT TOPIC — Concurrent SoC development and end-to-end planning (LA), p. 430.
DATE-2009-Fujita #challenge #design #question: Nano-electronics challenge chip designers meet real nano-electronics in 2010s? (SF), pp. 431–432.
DATE-2009-MatsunagaHIMEOH #in memory: MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues (SM, JH, SI, KM, TE, HO, TH), pp. 433–435.
DATE-2009-MitraZPW #logic #using: Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (SM, JZ, NP, HW), pp. 436–441.
DATE-2009-DongCC #configuration management #design: Reconfigurable circuit design with nanomaterials (CD, SC, DC), pp. 442–447.
DATE-2009-LiRJ #architecture: An architecture for secure software defined radio (CL, AR, NKJ), pp. 448–453.
DATE-2009-GuoS #bound #design #distributed #optimisation #using: Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage (XG, PS), pp. 454–459.
DATE-2009-DabiriP #hardware: Hardware aging-based software metering (FD, MP), pp. 460–465.
DATE-2009-JooKH #architecture #communication: On-chip communication architecture exploration for processor-pool-based MPSoC (YPJ, SK, SH), pp. 466–471.
DATE-2009-LukasiewyczSGHT #architecture #communication #synthesis: Combined system synthesis and communication architecture exploration for MPSoCs (ML, MS, MG, CH, JT), pp. 472–477.
DATE-2009-DensmoreSDPS #design #evaluation #framework #using: UMTS MPSoC design evaluation using a system level design framework (DD, AS, AD, RP, ALSV), pp. 478–483.
DATE-2009-VayrynenSL #execution #fault tolerance #multi #optimisation: Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (MV, VS, EL), pp. 484–489.
DATE-2009-PanKK #multi #reliability: Improving yield and reliability of chip multiprocessors (AP, OK, SK), pp. 490–495.
DATE-2009-YanHL #detection #fault #online: A unified online Fault Detection scheme via checking of Stability Violation (GY, YH, XL), pp. 496–501.
DATE-2009-LeveugleCMV #fault #injection #quantifier #statistics: Statistical fault injection: Quantified error and confidence (RL, AC, PM, PV), pp. 502–506.
DATE-2009-ChoSE #memory management #named #realtime: KAST: K-associative sector translation for NAND flash memory in real-time systems (HjC, DS, YIE), pp. 507–512.
DATE-2009-ViehlPBR #analysis #performance #scheduling: White box performance analysis considering static non-preemptive software scheduling (AV, MP, OB, WR), pp. 513–518.
DATE-2009-KonigBSMNW #behaviour #embedded #evaluation #performance #realtime: Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems (FK, DB, FS, UM, MN, GW), pp. 519–523.
DATE-2009-NegreanSE #analysis #multi: Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources (MN, SS, RE), pp. 524–529.
DATE-2009-GraciaMVBV #latency: Light NUCA: A proposal for bridging the inter-cache latency gap (DSG, TM, FV, RB, VV), pp. 530–535.
DATE-2009-FytrakiP #configuration management: ReSim, a trace-driven, reconfigurable ILP processor simulator (SF, DNP), pp. 536–541.
DATE-2009-AnsaloniBP #architecture #embedded: Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration (GA, PB, LP), pp. 542–547.
DATE-2009-GaluzziTMB #algorithm #automation: Algorithms for the automatic extension of an instruction-set (CG, DT, RM, KB), pp. 548–553.
DATE-2009-RistauLAF #analysis #parallel: Dimensioning heterogeneous MPSoCs via parallelism analysis (BR, TL, OA, GF), pp. 554–557.
DATE-2009-FiorinPS #monitoring #runtime: MPSoCs run-time monitoring through Networks-on-Chip (LF, GP, CS), pp. 558–561.
DATE-2009-LudoviciVMRGLGB #constraints #design: Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints (DL, FGV, SM, CGR, MEG, PL, GNG, DB), pp. 562–565.
DATE-2009-ModarressiSA #hybrid #network: A hybrid packet-circuit switched on-chip network based on SDM (MM, HSA, MA), pp. 566–569.
DATE-2009-SuCGSP #memory management #named #operating system: SecBus: Operating System controlled hierarchical page-based memory bus protection (LS, SC, PG, CS, RP), pp. 570–573.
DATE-2009-DiemerE #quality: A link arbitration scheme for quality of service in a latency-optimized network-on-chip (JD, RE), pp. 574–577.
DATE-2009-LuMJBWH #communication: Flow regulation for on-chip communication (ZL, MM, AJ, ACB, PvdW, TH), pp. 578–581.
DATE-2009-ChangBM #design #using: Customizing IP cores for system-on-chip designs using extensive external don’t-cares (KHC, VB, ILM), pp. 582–585.
DATE-2009-MrabtiPB #approach #design: Extending IP-XACT to support an MDE based approach for SoC design (AEM, FP, AB), pp. 586–589.
DATE-2009-GenzD: Overcoming limitations of the SystemC data introspection (CG, RD), pp. 590–593.
DATE-2009-XuVJ #runtime: Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage (HX, RV, WBJ), pp. 594–597.
DATE-2009-BardineCFGP #migration #power management: A power-efficient migration mechanism for D-NUCA caches (AB, MC, PF, GG, CAP), pp. 598–601.
DATE-2009-Garnier #challenge #roadmap: Trends and challenges in wireless application processors (PG), p. 603.
DATE-2009-GargM #3d #analysis #process #variability: System-level process variability analysis and mitigation for 3D MPSoCs (SG, DM), pp. 604–609.
DATE-2009-LeeKHBJFL #3d #co-evolution #design #network: Co-design of signal, power, and thermal distribution networks for 3D ICs (YJL, YJK, GH, MSB, YKJ, AGF, SKL), pp. 610–615.
DATE-2009-BobbaZPAM #design #logic #standard #synthesis: Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis (SB, JZ, AP, DA, GDM), pp. 616–621.
DATE-2009-JamaaMM #library #logic #multi #novel #synthesis: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (MHBJ, KM, GDM), pp. 622–627.
DATE-2009-RealVD #correlation #using: Enhancing correlation electromagnetic attack using planar near-field cartography (DR, FV, MD), pp. 628–633.
DATE-2009-LomneMTRSC #evaluation #logic #robust: Evaluation on FPGA of triple rail logic robustness against DPA and DEMA (VL, PM, LT, MR, RS, NC), pp. 634–639.
DATE-2009-SauvageGDMN #constraints: Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints (LS, SG, JLD, YM, MN), pp. 640–645.
DATE-2009-HenzenCFF #evaluation #hardware: Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT (LH, FC, NF, WF), pp. 646–651.
DATE-2009-GhoseGDAW #architecture #detection #memory management: Architectural support for low overhead detection of memory violations (SG, LG, PD, AA, CW), pp. 652–657.
DATE-2009-WagnerB #hardware #manycore #named: Caspar: Hardware patching for multicore processors (IW, VB), pp. 658–663.
DATE-2009-Cilardo #architecture: A new speculative addition architecture suitable for two’s complement operations (AC), pp. 664–669.
DATE-2009-LangenJ: Limiting the number of dirty cache lines (PJdL, BHHJ), pp. 670–675.
DATE-2009-MarinissenLHSMSP #question #testing: Contactless testing: Possibility or pipe-dream? (EJM, DYL, JPH, CS, BM, SS, LP), pp. 676–681.
DATE-2009-IzosimovPPEP #analysis #embedded #fault tolerance #optimisation: Analysis and optimization of fault-tolerant embedded systems with hardened processors (VI, IP, PP, PE, ZP), pp. 682–687.
DATE-2009-FahmyRJ #bound #distributed #memory management #multi #on the #realtime #transaction: On bounding response times under software transactional memory in distributed multiprocessor real-time systems (SFF, BR, EDJ), pp. 688–693.
DATE-2009-YangCKT #approximate #energy #multi #realtime #scheduling: An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems (CYY, JJC, TWK, LT), pp. 694–699.
DATE-2009-DasV #approach #automation #design #grammarware #graph grammar #multi: A graph grammar based approach to automated multi-objective analog circuit design (AD, RV), pp. 700–705.
DATE-2009-PalmersMSG #multi: Massively multi-topology sizing of analog integrated circuits (PP, TM, MS, GGEG), pp. 706–711.
DATE-2009-AliKWW #modelling #optimisation #performance: Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits (SA, LK, RW, PRW), pp. 712–717.
DATE-2009-TannirK #analysis #using: Computation of IP3 using single-tone moments analysis (DT, RK), pp. 718–723.
DATE-2009-BarkeGGHHPSW #formal method #verification: Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
DATE-2009-LiC #architecture #bibliography #memory management #tool support: An overview of non-volatile memory technology and the implication for tools and architectures (HL, YC), pp. 731–736.
DATE-2009-WuLZSX #hybrid #performance: Power and performance of read-write aware Hybrid Caches with non-volatile memories (XW, JL, LZ, ES, YX), pp. 737–742.
DATE-2009-RobertsKM #energy #memory management #using: Using non-volatile memory to save energy in servers (DR, TK, TNM), pp. 743–748.
DATE-2009-ConcerIB #algorithm #named #network #novel: aEqualized: A novel routing algorithm for the Spidergon Network On Chip (NC, SI, LB), pp. 749–754.
DATE-2009-ZuoFQWJNLYB #manycore: Group-caching for NoC based multicore cache coherent systems (ZW, FS, QZ, WJ, JL, ND, LX, YAT, BQ), pp. 755–760.
DATE-2009-MadduriVBT #manycore #monitoring: A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.
DATE-2009-BeltrameFS #design #realtime: A real-time application design methodology for MPSoCs (GB, LF, DS), pp. 767–772.
DATE-2009-KandemirZO #adaptation #multi: Adaptive prefetching for shared cache based chip multiprocessors (MTK, YZ, ÖÖ), pp. 773–778.
DATE-2009-PatelPR #architecture #framework #named #security: CUFFS: An instruction count based architectural framework for security of MPSoCs (KP, SP, RGR), pp. 779–784.
DATE-2009-HolcombLS #analysis #design #fault: Design as you see FIT: System-level soft error analysis of sequential circuits (DEH, WL, SAS), pp. 785–790.
DATE-2009-AlvesNDB #detection #fault #multi #using: Detecting errors using multi-cycle invariance information (NA, KN, JD, RIB), pp. 791–796.
DATE-2009-LuGUH #approach #development #novel: A novel approach to entirely integrate Virtual Test into test development flow (PL, DG, GU, KH), pp. 797–802.
DATE-2009-LombardiMB #clustering #manycore #realtime #robust #scheduling: Robust non-preemptive hard real-time scheduling for clustered multicore platforms (ML, MM, LB), pp. 803–808.
DATE-2009-MarongiuB #memory management #performance: Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy (AM, LB), pp. 809–814.
DATE-2009-SafizadehTATB #nondeterminism #using: Using randomization to cope with circuit uncertainty (HS, MT, EKA, GT, KB), pp. 815–820.
DATE-2009-HongNKO #concurrent #multi #process #thread: Process variation aware thread mapping for Chip Multiprocessors (SH, SHKN, MTK, ÖÖ), pp. 821–826.
DATE-2009-Held #design #scalability: Gate sizing for large cell-based designs (SH), pp. 827–832.
DATE-2009-MohammadZadehMJZ #multi #network: Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network (NM, MM, AJ, MSZ), pp. 833–838.
DATE-2009-TaoL #grid #power management: Decoupling capacitor planning with analytical delay model on RLC power grid (YT, SKL), pp. 839–844.
DATE-2009-LuCLS #co-evolution #design: Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design (CHL, HMC, CNJL, WYS), pp. 845–850.
DATE-2009-RichterJE #framework #learning #verification: Learning early-stage platform dimensioning from late-stage timing verification (KR, MJ, RE), pp. 851–857.
DATE-2009-ReicheltST #constraints #design #realtime: The influence of real-time constraints on the design of FlexRay-based systems (SR, OS, GT), pp. 858–863.
DATE-2009-FerrariNGRG #component #implementation #memory management #trade-off: Time and memory tradeoffs in the implementation of AUTOSAR components (AF, MDN, GG, GR, PG), pp. 864–869.
DATE-2009-BhagawatDC #architecture #detection: Systolic like soft-detection architecture for 4×4 64-QAM MIMO system (PB, RD, GC), pp. 870–873.
DATE-2009-FourmigueGNA #design #framework #protocol: Co-simulation based platform for wireless protocols design explorations (AF, BG, GN, EMA), pp. 874–877.
DATE-2009-Dubrova #how: How to speed-up your NLFSR-based stream cipher (ED), pp. 878–881.
DATE-2009-TasdizenKAH #architecture #configuration management #estimation #hardware #performance: A high performance reconfigurable Motion Estimation hardware architecture (OT, HK, AA, IH), pp. 882–885.
DATE-2009-PotterLC #configuration management #design: Partition-based exploration for reconfigurable JPEG designs (PGP, WL, PYKC), pp. 886–889.
DATE-2009-HaastregtK #automation #c #hardware #network #process #streaming #synthesis: Automated synthesis of streaming C applications to process networks in hardware (SvH, BK), pp. 890–893.
DATE-2009-BarontiLRS #detection #distributed #metric: Distributed sensor for steering wheel rip force measurement in driver fatigue detection (FB, FL, RR, RS), pp. 894–897.
DATE-2009-GarciaO #embedded #fault #information management #self: Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy (SG, AO), pp. 898–901.
DATE-2009-WangW #machine learning: Machine learning-based volume diagnosis (SW, WW), pp. 902–905.
DATE-2009-PaternaBAPDO #adaptation #multi: Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip (FP, LB, AA, FP, GD, MO), pp. 906–909.
DATE-2009-SasanHEK #process #scalability: Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (AS, HH, AME, FJK), pp. 911–916.
DATE-2009-SinghPHMM #embedded #power management: Single ended 6T SRAM with isolated read-port for low-power embedded systems (JS, DKP, SH, SPM, JM), pp. 917–922.
DATE-2009-FacchiniCVPCDBM #3d #evaluation #mobile #performance: System-level power/performance evaluation of 3D stacked DRAMs for mobile applications (MF, TC, AV, MP, FC, WD, LB, PM), pp. 923–928.
DATE-2009-VignonCDMF #3d #architecture #novel: A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context (AV, SC, WD, PM, MF), pp. 929–933.
DATE-2009-AhoNTK #multi #video: A case for multi-channel memories in video recording (EA, JN, PAT, KK), pp. 934–939.
DATE-2009-ZridaJAA #implementation #parallel #video: High level H.264/AVC video encoder parallelization for multiprocessor implementation (HKZ, AJ, ACA, MA), pp. 940–945.
DATE-2009-YeoK #behaviour #manycore: Temperature-aware scheduler based on thermal behavior grouping in multicore systems (IY, EJK), pp. 946–951.
DATE-2009-KhanK09a #architecture #co-evolution #design #hardware #multi: Hardware/software co-design architecture for thermal management of chip multiprocessors (OK, SK), pp. 952–957.
DATE-2009-BauerSH #architecture #configuration management #design: Cross-architectural design space exploration tool for reconfigurable processors (LB, MS, JH), pp. 958–963.
DATE-2009-BruneelAS #automation #configuration management #framework #self: Automatically mapping applications to a self-reconfiguring platform (KB, FA, DS), pp. 964–969.
DATE-2009-SchallenbergNHHO #configuration management #framework #modelling #synthesis: OSSS+R: A framework for application level modelling and synthesis of reconfigurable systems (AS, WN, AH, PAH, FO), pp. 970–975.
DATE-2009-KoesterLHP #configuration management #design #optimisation: Design optimizations to improve placeability of partial reconfiguration modules (MK, WL, JH, MP), pp. 976–981.
DATE-2009-YangNV #automation #data analysis #debugging: Automated data analysis solutions to silicon debug (YSY, NN, AGV), pp. 982–987.
DATE-2009-LadharMB #fault #performance: Efficient and accurate method for intra-gate defect diagnoses in nanometer technology and volume data (AL, MM, LB), pp. 988–993.
DATE-2009-PomeranzR #fault: Selection of a fault model for fault diagnosis based on unique responses (IP, SMR), pp. 994–999.
DATE-2009-TangGCR #generative #multi: Improving compressed test pattern generation for multiple scan chain failure diagnosis (XT, RG, WTC, SMR), pp. 1000–1005.
DATE-2009-LeonardiPC #case study #deployment #distributed #embedded #network: A case study in distributed deployment of embedded software for camera networks (FL, AP, LPC), pp. 1006–1011.
DATE-2009-ChangHL #adaptation #concurrent #embedded #manycore #named #testing: pTest: An adaptive testing tool for concurrent software on embedded multicore processors (SWC, KYH, JKL), pp. 1012–1017.
DATE-2009-SahuBP #concurrent #estimation #framework #multi #performance #thread: A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors (AS, MB, PRP), pp. 1018–1023.
DATE-2009-FummiPR #design #embedded #middleware: Networked embedded system applications design driven by an abstract middleware environment (FF, GP, NR), pp. 1024–1029.
DATE-2009-EberleMNGCBTV #challenge: Health-care electronics The market, the challenges, the progress (WE, ASM, TKTN, GGEG, RC, AB, CT, BV), pp. 1030–1034.
DATE-2009-KodakaSTONKMUAOKTM #design #implementation #manycore #scalability #thread: Design and implementation of scalable, transparent threads for multi-core media processor (TK, SS, TT, RO, NN, KK, TM, YU, HA, YO, TK, YT, NM), pp. 1035–1039.
DATE-2009-KasperskiPDS #architecture #configuration management #development #flexibility: High data rate fully flexible SDR modem advanced configurable architecture & development methodology (FK, OP, FD, MS), pp. 1040–1044.
DATE-2009-BonnaudS #design: Cross-coupling in 65nm fully integrated EDGE System On Chip Design and cross-coupling prevention of complex 65nm SoC (PHB, GS), pp. 1045–1050.
DATE-2009-JerrayaN #comprehension #embedded #manycore #tutorial: Embedded tutorial — Understanding multicore technologies (AAJ, GN), p. 1051.
DATE-2009-LiWSDS #communication #latency: Latency criticality aware on-chip communication (ZL, JW, LS, RPD, YS), pp. 1052–1057.
DATE-2009-KwonYUJ #performance #problem: In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem (WCK, SY, JU, SWJ), pp. 1058–1063.
DATE-2009-EbrahimiDNMAPT #multi #protocol: An efficent dynamic multicast routing protocol for distributing traffic in NOCs (ME, MD, MHN, SM, AAK, JP, HT), pp. 1064–1069.
DATE-2009-MillbergJ #worst-case: Priority based forced requeue to reduce worst-case latencies for bursty traffic (MM, AJ), pp. 1070–1075.
DATE-2009-LiNZGSS #dependence #optimisation #protocol: Optimizations of an application-level protocol for enhanced dependability in FlexRay (WL, MDN, WZ, PG, ALSV, SAS), pp. 1076–1081.
DATE-2009-ArmengaudS #metric #network: Remote measurement of local oscillator drifts in FlexRay networks (EA, AS), pp. 1082–1087.
DATE-2009-ZiermannWT #network #protocol: CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates (TZ, SW, JT), pp. 1088–1093.
DATE-2009-MarchettiFRM: Shock immunity enhancement via resonance damping in gyroscopes for automotive applications (EM, LF, AR, MDM), pp. 1094–1099.
DATE-2009-MadridSNGAVMA #framework #integration: Integration of an advanced emergency call subsystem into a car-gateway platform (NMM, RS, ARN, JSG, AlSA, PSV, CRM, FA), pp. 1100–1105.
DATE-2009-KinsmanN #finite #modulo theories #precise #using: Finite Precision bit-width allocation using SAT-Modulo Theory (ABK, NN), pp. 1106–1111.
DATE-2009-PaikSS #named #performance #synthesis: HLS-l: High-level synthesis of high performance latch-based circuits (SP, IS, YS), pp. 1112–1117.
DATE-2009-MilderHP #automation #generative #permutation #streaming: Automatic generation of streaming datapaths for arbitrary fixed permutations (PAM, JCH, MP), pp. 1118–1123.
DATE-2009-GolshanB #composition #design: SEU-aware resource binding for modular redundancy based designs on FPGAs (SG, EB), pp. 1124–1129.
DATE-2009-KavousianosC #fault #generative #testing: Generation of compact test sets with high defect coverage (XK, KC), pp. 1130–1135.
DATE-2009-RemersaroRRP #generative #scalability #testing: A scalable method for the generation of small test sets (SR, JR, SMR, IP), pp. 1136–1141.
DATE-2009-TzengH #named: QC-Fill: An X-Fill method for quick-and-cool scan test (CWT, SYH), pp. 1142–1147.
DATE-2009-BaertBWA #using: Exploring parallelizations of applications for MPSoC platforms using MPA (RB, EB, SW, TJA), pp. 1148–1153.
DATE-2009-MazziniPV #development #realtime: An MDE methodology for the development of high-integrity real-time systems (SM, SP, TV), pp. 1154–1159.
DATE-2009-BordeHP #architecture #component #configuration management: Mode-based reconfiguration of critical software component architectures (EB, GH, LP), pp. 1160–1165.
DATE-2009-YangHMP #behaviour #semantics #towards: Towards a formal semantics for the AADL behavior annex (ZY, KH, DM, LP), pp. 1166–1171.
DATE-2009-VillenaCIS #modelling #on the #parametricity #performance #reduction: On the efficient reduction of complete EM based parametric models (JFV, GC, DI, LMS), pp. 1172–1177.
DATE-2009-HatamiFAP #library #performance: Efficient compression and handling of current source model library waveforms (SH, PF, SA, MP), pp. 1178–1183.
DATE-2009-ChenW #3d #modelling #simulation: New simulation methodology of 3D surface roughness loss for interconnects modeling (QC, NW), pp. 1184–1189.
DATE-2009-WangCTHR #modelling #optimisation #performance #polynomial #using: An efficient decoupling capacitance optimization using piecewise polynomial models (XW, YC, SXDT, XH, JR), pp. 1190–1195.
DATE-2009-OetjensGGN #automation #hardware #process: An automated flow for integrating hardware IP into the automotive systems engineering process (JHO, RG, JG, WN), pp. 1196–1201.
DATE-2009-Perry #design #modelling #quality #synthesis: Model Based Design needs high level synthesis — A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design (SP), pp. 1202–1207.
DATE-2009-DoriolVFRGP #design: EMC-aware design on a microcontroller for automotive applications (PJD, YV, CF, MR, GG, DP), pp. 1208–1213.
DATE-2009-LettninNBRGKRSR #hardware #verification: Semiformal verification of temporal properties in automotive hardware dependent software (DL, PKN, JB, JR, JG, TK, WR, VS, SR), pp. 1214–1217.
DATE-2009-Schat #fault #on the: On the relationship between stuck-at fault coverage and transition fault coverage (JS), pp. 1218–1221.
DATE-2009-GhermanECSB: System-level hardware-based protection of memories against soft-errors (VG, SE, MC, NS, YB), pp. 1222–1225.
DATE-2009-AbateSVK #case study #functional: A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (FA, LS, MV, FLK), pp. 1226–1229.
DATE-2009-NovoLBPC #finite #precise: Finite precision processing in wireless applications (DN, ML, BB, LVdP, FC), pp. 1230–1233.
DATE-2009-HsiehLH #reduction: A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test (WWH, ISL, TH), pp. 1234–1237.
DATE-2009-MaricauG #performance #reliability #simulation #variability: Efficient reliability simulation of analog ICs including variability and time-varying stress (EM, GGEG), pp. 1238–1241.
DATE-2009-DemangelFDCW #architecture: A generic architecture of CCSDS Low Density Parity Check decoder for near-earth applications (FD, NF, ND, FC, CW), pp. 1242–1245.
DATE-2009-KuhneGD #analysis #comprehension #design: Property analysis and design understanding (UK, DG, RD), pp. 1246–1249.
DATE-2009-KochteZIKRWCP #modelling #transaction #using #validation: Test exploration and validation using transaction level models (MAK, CGZ, MEI, RSK, MR, HJW, SDC, PP), pp. 1250–1253.
DATE-2009-KolligOH #framework #manycore: Heterogeneous multi-core platform for consumer multimedia applications (PK, CO, TH), pp. 1254–1259.
DATE-2009-Berkel #manycore #mobile: Multi-core for mobile phones (CHvB), pp. 1260–1265.
DATE-2009-Flamand #manycore #towards: Strategic directions towards multicore application specific computing (EF), p. 1266.
DATE-2009-LongLFDY #adaptation #clustering #energy #network: Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks (HL, YL, XF, RPD, HY), pp. 1267–1272.
DATE-2009-SubramanianGD #adaptation #configuration management #design #embedded #grid #network #online #policy: Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes (VS, MG, AD), pp. 1273–1278.
DATE-2009-ZhengH #array #logic #programmable #satisfiability: Defect-aware logic mapping for nanowire-based programmable logic arrays via satisfiability (YZ, CH), pp. 1279–1283.
DATE-2009-WilleGFDD #debugging #network: Debugging of Toffoli networks (RW, DG, SF, GWD, RD), pp. 1284–1289.
DATE-2009-ZhaoC: Cross-contamination avoidance for droplet routing in digital microfluidic biochips (YZ, KC), pp. 1290–1295.
DATE-2009-0001BW #case study #fault #network: Error correction in single-hop wireless sensor networks — A case study (DS, MB, NW), pp. 1296–1301.
DATE-2009-GuanLF #design #scalability #set: Design of an application-specific instruction set processor for high-throughput and scalable FFT (XG, HL, YF), pp. 1302–1307.
DATE-2009-0004SKAKW #novel: A novel LDPC decoder for DVB-S2 IP (SM, MS, MK, MA, FK, NW), pp. 1308–1313.
DATE-2009-GuntoroG #flexibility #float: A flexible floating-point wavelet transform and wavelet packet processor (AG, MG), pp. 1314–1319.
DATE-2009-LiCSSS #analysis #on the #statistics: On hierarchical statistical static timing analysis (BL, NC, MS, WS, US), pp. 1320–1325.
DATE-2009-SulflowFBKD #debugging #satisfiability: Increasing the accuracy of SAT-based debugging (AS, GF, CB, UK, RD), pp. 1326–1331.
DATE-2009-ChatterjeeDB #named #simulation: GCS: High-performance gate-level simulation with GPGPUs (DC, AD, VB), pp. 1332–1337.
DATE-2009-LiuX #validation: Trace signal selection for visibility enhancement in post-silicon validation (XL, QX), pp. 1338–1343.
DATE-2009-NeyDGPVBG #fault: A new design-for-test technique for SRAM core-cell stability faults (AN, LD, PG, SP, AV, MB, VG), pp. 1344–1348.
DATE-2009-KhursheedAH #design #fault #multi #reduction: Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (SSK, BMAH, PH), pp. 1349–1354.
DATE-2009-HolstW #algorithm: A diagnosis algorithm for extreme space compaction (SH, HJW), pp. 1355–1360.
DATE-2009-HsiehH #3d #design #memory management: Thermal-aware memory mapping in 3D designs (ACH, TH), pp. 1361–1366.
DATE-2009-LeeS #fault #static analysis: Static analysis to mitigate soft errors in register files (JL, AS), pp. 1367–1372.
DATE-2009-OzturkK #compilation #execution #memory management #using: Using dynamic compilation for continuing execution under reduced memory availability (ÖÖ, MTK), pp. 1373–1378.
DATE-2009-KeCG #configuration management #design: A design methodology for fully reconfigurable Delta-Sigma data converters (YK, JC, GGEG), pp. 1379–1384.
DATE-2009-WilsonW #configuration management #variability: Optimal sizing of configurable devices to reduce variability in integrated circuits (PRW, RW), pp. 1385–1390.
DATE-2009-WangKABZ #automation #design #energy: An automated design flow for vibration-based energy harvester systems (LW, TJK, BMAH, SPB, DZ), pp. 1391–1396.
DATE-2009-LinHL #design: Enhanced design of filterless class-D audio amplifier (CWL, BSH, YCL), pp. 1397–1402.
DATE-2009-PaciBB #adaptation #bias #communication #effectiveness #variability: Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (GP, DB, LB), pp. 1404–1409.
DATE-2009-CoskunAARL #3d #architecture #manycore: Dynamic thermal management in 3D multicore architectures (AKC, JLA, DA, TSR, YL), pp. 1410–1415.
DATE-2009-DabiriVPS #energy #realtime: Energy minimization for real-time systems with non-convex and discrete operation modes (FD, AV, MP, MS), pp. 1416–1421.
DATE-2009-WangHZC #design: Exploiting narrow-width values for thermal-aware register file designs (SW, JSH, SGZ, SWC), pp. 1422–1427.
DATE-2009-BartoliniRB #analysis #quality #scalability #visual notation: Visual quality analysis for dynamic backlight scaling in LCD systems (AB, MR, LB), pp. 1428–1433.
DATE-2009-ShafiqueBH #approach #design #hardware #parallel #performance #predict #video: A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec (MS, LB, JH), pp. 1434–1439.
DATE-2009-IqbalH #performance: Efficient constant-time entropy decoding for H.264 (NI, JH), pp. 1440–1445.
DATE-2009-BellasiFS #analysis #modelling #multi #power management #predict: Predictive models for multimedia applications power consumption based on use-case and OS level analysis (PB, WF, DS), pp. 1446–1451.
DATE-2009-GopalakrishnanK #algebra #polynomial #synthesis: Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis (SG, PK), pp. 1452–1457.
DATE-2009-KravetsM #logic #synthesis #using: Sequential logic synthesis using symbolic bi-decomposition (VNK, AM), pp. 1458–1463.
DATE-2009-BernasconiCTV #on the: On decomposing Boolean functions via extended cofactoring (AB, VC, GT, TV), pp. 1464–1469.
DATE-2009-ChiangOY: Register placement for high-performance circuits (MFC, TO, TY), pp. 1470–1475.
DATE-2009-ChandraKK #adaptation #scalability: Scalable Adaptive Scan (SAS) (AC, RK, YK), pp. 1476–1481.
DATE-2009-KoutsoupiaKKN #self #testing: LFSR-based test-data compression with self-stoppable seeds (MK, EK, XK, DN), pp. 1482–1487.
DATE-2009-YilmazC #detection #fault: Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects (MY, KC), pp. 1488–1493.
DATE-2009-LiuX09a #framework #reduction: A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment (XL, QX), pp. 1494–1499.
DATE-2009-BombieriFPV #generative: Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.
DATE-2009-ZhuSJ #architecture #cpu #hybrid #realtime #scheduling #streaming: Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures (JZ, IS, AJ), pp. 1506–1511.
DATE-2009-MukherjeeAPMD #approach #behaviour #formal method #generative: A formal approach for specification-driven AMS behavioral model generation (SM, AA, SKP, RM, PD), pp. 1512–1517.
DATE-2009-MadlenerMH #named #performance: SC-DEVS: An efficient SystemC extension for the DEVS model of computation (FM, HGM, SAH), pp. 1518–1523.
DATE-2009-BaeMV #scheduling: Exploiting clock skew scheduling for FPGA (SB, PM, NV), pp. 1524–1529.
DATE-2009-ChenKLA: Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing (XC, JK, SL, VA), pp. 1530–1535.
DATE-2009-HuynhM #configuration management #embedded #realtime #runtime: Runtime reconfiguration of custom instructions for real-time embedded systems (HPH, TM), pp. 1536–1541.
DATE-2009-SchlichtmannSKPGDEH #design #how #statistics: Digital design at a crossroads How to make statistical design methodologies industrially relevant (US, MS, HK, MP, VG, MD, UE, JH), pp. 1542–1547.
DATE-2009-HanumaiahVC #constraints #manycore #performance: Performance optimal speed control of multi-core processors under thermal constraints (VH, SBKV, KSC), pp. 1548–1551.
DATE-2009-PelcatMAN #architecture #manycore #scalability: Scalable compile-time scheduler for multi-core architectures (MP, PM, SA, JFN), pp. 1552–1555.
DATE-2009-SartoriK #architecture #distributed #manycore #power management: Distributed peak power management for many-core architectures (JS, RK), pp. 1556–1559.
DATE-2009-BraunesS #generative: Generating the trace qualification configuration for MCDS from a high level language (JB, RGS), pp. 1560–1563.
DATE-2009-PuschiniCBST #distributed #energy #latency: Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC (DP, FC, PB, GS, LT), pp. 1564–1567.
DATE-2009-CostaM #approach #embedded: A MILP-based approach to path sensitization of embedded software (JCC, JCM), pp. 1568–1571.
DATE-2009-GregertsenS #ada #multi #performance #runtime: An efficient and deterministic multi-tasking run-time environment for Ada and the Ravenscar profile on the Atmel AVR®32 UC3 microcontroller (KNG, AS), pp. 1572–1575.
DATE-2009-SabeghiB #approach #configuration management #runtime #towards: Toward a runtime system for reconfigurable computers: A virtualization approach (MS, KB), pp. 1576–1579.
DATE-2009-VecchieTS #compilation #execution #imperative: Separate compilation and execution of imperative synchronous modules (EV, JPT, KS), pp. 1580–1583.
DATE-2009-LeupersVBHDN #exclamation #programming: Programming MPSoC platforms: Road works ahead! (RL, AV, MB, SH, RD, AN), pp. 1584–1589.
DATE-2009-ChambersMV #generative #performance #satisfiability: Faster SAT solving with better CNF generation (BC, PM, DV), pp. 1590–1595.
DATE-2009-PigorschS: Exploiting structure in an AIG based QBF solver (FP, CS), pp. 1596–1601.
DATE-2009-HeH #algorithm #encoding #performance #verification: An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification (NH, MSH), pp. 1602–1607.
DATE-2009-LiFNBPC #architecture #co-evolution #design #detection #ml #parallel #set: Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors (ML, RF, DN, BB, LVdP, FC), pp. 1608–1613.
DATE-2009-BachmannGHBS #power management: A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing (CB, AG, JH, MB, CS), pp. 1614–1619.
DATE-2009-JafriKBJ #flexibility #linear: ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications (ARJ, DK, AB, MJ), pp. 1620–1625.
DATE-2009-GarridoVSML #detection #implementation: Implementation of a reduced-lattice MIMO detector for OFDM Systems (JSG, HV, MS, DM, AL), pp. 1626–1631.
DATE-2009-ZabelM #injection #simulation: Increased accuracy through noise injection in abstract RTOS simulation (HZ, WM), pp. 1632–1637.
DATE-2009-FummiPQA #energy #flexibility #network #simulation: Flexible energy-aware simulation of heterogenous wireless sensor networks (FF, GP, DQ, AA), pp. 1638–1643.
DATE-2009-DarbariAFB #design #simulation #using: Selective state retention design using symbolic simulation (AD, BMAH, DF, JB), pp. 1644–1649.
DATE-2009-KorhonenK #identification: A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique (EK, JK), pp. 1650–1655.
DATE-2009-GoyalSC #novel #self: A novel self-healing methodology for RF Amplifier circuits based on oscillation principles (AG, MS, AC), pp. 1656–1661.
DATE-2009-MullerWJSM #approach #linear #modelling #testing: An approach to linear model-based testing for nonlinear cascaded mixed-signal systems (RM, CW, HJJ, SS, HM), pp. 1662–1667.
DATE-2009-StratigopoulosMM #set: Enrichment of limited training sets in machine-learning-based analog/RF test (HGDS, SM, YM), pp. 1668–1673.
DATE-2009-MonyBMB #identification #scalability: Speculative reduction-based scalable redundancy identification (HM, JB, AM, RKB), pp. 1674–1679.
DATE-2009-BaumgartnerM #liveness #scalability: Scalable liveness checking via property-preserving transformations (JB, HM), pp. 1680–1685.
DATE-2009-CabodiCGMNQ #constraints #model checking #verification: Speeding up model checking by exploiting explicit and hidden verification constraints (GC, PC, LG, MM, SN, SQ), pp. 1686–1691.
DATE-2009-PurandareWK #abstraction #refinement #using: Strengthening properties using abstraction refinement (MP, TW, DK), pp. 1692–1697.
DATE-2009-YangSVBS #approximate #logic: Sequential logic rectifications with approximate SPFDs (YSY, SS, AGV, RKB, DES), pp. 1698–1703.
DATE-2009-BaneresCK #design: Variable-latency design by function speculation (DB, JC, MK), pp. 1704–1709.
DATE-2009-DSilvaK #detection #fixpoint #multi: Fixed points for multi-cycle path detection (VD, DK), pp. 1710–1715.

Proceedings of the 13th Conference on Design, Automation and Test in EuropeDATE, 2009.

Contents (310 items)

Proceedings of the 13th Conference on Design, Automation and Test in Europe
DATE, 2009.