1 × France
1 × Germany
1 × USA
A.Nayak A.N.Choudhary P.Banerjee G.Singh S.Prabhakar B.Dwivedi A.Ghosh
fpgas (2) construct (1) synthesi (1) hardwar (1) concret (1) analysi (1) precis (1) matlab (1) applic (1) verif (1)
Person: Malay Haldar
Wrote 3 papers:
- DAC-2008-HaldarSPDG #c++ #modelling #verification
- Construction of concrete verification models from C++ (MH, GS, SP, BD, AG), pp. 942–947.
- Accurate Area and Delay Estimators for FPGAs (AN, MH, ANC, PB), pp. 862–869.
- DATE-2001-NayakHCB #analysis #automation #fault #hardware #matlab #precise #synthesis
- Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.