Stem fpgas$ (all stems)

107 papers:

DAC-2015-ChenC #architecture

Routing-architecture-aware analytical placement for heterogeneous FPGAs (SYC, YWC), p. 6.

DAC-2015-HeyseS

Avoiding transitional effects in dynamic circuit specialisation on FPGAs (KH, DS), p. 6.

DAC-2015-RozicYDV #generative #performance #random

Highly efficient entropy extraction for true random number generators on FPGAs (VR, BY, WD, IV), p. 6.

ASPLOS-2015-TanQCAP #named #network #using

DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs (ZT, ZQ, XC, KA, DAP), pp. 207–221.

DAC-2014-RaoEST #multi #using

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes (PMBR, ME, RS, MBT), p. 6.

DAC-2013-GoncalvesPPD

Non-volatile FPGAs based on spintronic devices (OG, GP, GdP, BD), p. 3.

DAC-2013-LinBC #effectiveness #performance

An efficient and effective analytical placer for FPGAs (THL, PB, YWC), p. 6.

DAC-2013-PapakonstantinouCHCL #kernel #migration

Throughput-oriented kernel porting onto FPGAs (AP, DC, WmWH, JC, YL), p. 10.

DATE-2013-ChenLSCCAN #embedded #modelling #synthesis

High-level modeling and synthesis for embedded FPGAs (XC, SL, JS, TC, AC, GA, TGN), pp. 1565–1570.

VLDB-2013-NajafiSJ #flexibility #query

Flexible Query Processor on FPGAs (MN, MS, HAJ), pp. 1310–1313.

DATE-2012-AksoyCFM #design #finite

Design of low-complexity digital finite impulse response filters on FPGAs (LA, EC, PFF, JCM), pp. 1197–1202.

DATE-2012-CherkaouiFAF #comparison #self

Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs (AC, VF, AA, LF), pp. 1325–1330.

DATE-2012-HuangHLLLG #power management

Off-path leakage power aware routing for SRAM-based FPGAs (KH, YH, XL, BL, HL, JG), pp. 87–92.

DATE-2012-PomataMTRL #design #performance

Exploiting binary translation for fast ASIP design space exploration on FPGAs (SP, PM, GT, LR, ML), pp. 566–569.

SIGMOD-2012-TeubnerWN #automaton #configuration management

Skeleton automata for FPGAs: reconfiguring without reconstructing (JT, LW, CN), pp. 229–240.

DAC-2011-KesturIPANC #architecture #co-evolution #design #framework #re-engineering #using

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs (SK, KMI, SP, AAM, VN, CC), pp. 585–590.

DATE-2011-ChenLH #3d #architecture #towards

Architectural exploration of 3D FPGAs towards a better balance between area and delay (CIC, BCL, JDH), pp. 587–590.

DATE-2011-MeyerNHBSGSB #configuration management #performance #using

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration (JM, JN, MH, LB, OS, RMG, RS, JB), pp. 1542–1547.

DATE-2011-RoyRM #algorithm #modelling #performance

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs (SSR, CR, DM), pp. 1231–1236.

DATE-2011-SterponeCMWF #configuration management #power management

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.

DATE-2011-VidalLGDG #configuration management #design #implementation #uml

Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation (JV, FdL, GG, JPD, SG), pp. 1208–1211.

DATE-2011-VissersNN #interface #realtime #synthesis #tool support #using

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools (KAV, SN, JN), pp. 848–850.

DAC-2010-ElizehN #embedded #memory management

Embedded memory binding in FPGAs (KE, NN), pp. 457–462.

DATE-2010-BsoulMS #process

Reliability- and process variation-aware placement for FPGAs (AAMB, NM, LS), pp. 1809–1814.

DATE-2010-HallerB #low cost #performance

High-speed clock recovery for low-cost FPGAs (IH, ZFB), pp. 610–613.

DATE-2010-SterponeB #algorithm #multi

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs (LS, NB), pp. 1231–1236.

DATE-2010-ZhuSJ #configuration management #cpu #design #performance #streaming

Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs (JZ, IS, AJ), pp. 1035–1040.

VLDB-2010-WoodsTA #detection

Complex Event Detection at Wire Speed with FPGAs (LW, JT, GA), pp. 660–669.

SAC-2010-AnastasiadisSP #detection #multi #performance

A fast multiplier-less edge detection accelerator for FPGAs (NA, IS, KZP), pp. 510–515.

DAC-2009-EllithorpeTK #architecture #named #network #using

Internet-in-a-Box: emulating datacenter network architectures using FPGAs (JDE, ZT, RHK), pp. 880–883.

DAC-2009-HagiescuWBR

A computing origami: folding streams in FPGAs (AH, WFW, DFB, RMR), pp. 282–287.

DATE-2009-AbateSVK #case study #functional

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs (FA, LS, MV, FLK), pp. 1226–1229.

DATE-2009-FlynnGG #configuration management

Bitstream relocation with local clock domains for partially reconfigurable FPGAs (AF, AGR, ADG), pp. 300–303.

DATE-2009-GolshanB #composition #design

SEU-aware resource binding for modular redundancy based designs on FPGAs (SG, EB), pp. 1124–1129.

DATE-2009-SioziosPS #3d #architecture

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs (KS, VFP, DS), pp. 172–177.

VLDB-2009-MuellerTA

Data Processing on FPGAs (RM, JT, GA), pp. 910–921.

VLDB-2009-MullerTA #compilation #query

Streams on Wires — A Query Compiler for FPGAs (RM, JT, GA), pp. 229–240.

DAC-2008-BijanskyA #named

TuneFPGA: post-silicon tuning of dual-Vdd FPGAs (SB, AA), pp. 796–799.

DAC-2008-CzajkowskiB #composition #linear #logic #synthesis

Functionally linear decomposition and synthesis of logic circuits for FPGAs (TSC, SDB), pp. 18–23.

DATE-2008-NeumannSBN #architecture #design #embedded #flexibility

Design flow for embedded FPGAs based on a flexible architecture template (BN, TvS, HB, TGN), pp. 56–61.

DATE-2008-Parandeh-AfsharBI #integer #linear #programming #synthesis

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming (HPA, PB, PI), pp. 1256–1261.

DATE-2008-PaulssonHB #integration #metric #power management

Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs (KP, MH, JB), pp. 50–55.

DATE-2008-SterponeATG #design #fault tolerance #on the #safety

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications (LS, MAA, JNT, HGM), pp. 336–341.

CC-2008-BergeronFD #compilation #configuration management #hardware #jit #off the shelf

Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs (EB, MF, JPD), pp. 178–192.

DAC-2007-ChengCW07a #named #synthesis

DDBDD: Delay-Driven BDD Synthesis for FPGAs (LC, DC, MDFW), pp. 910–915.

DAC-2007-LucasHE #library #named #realtime

FlexWAFE — A High-end Real-Time Stream Processing Library for FPGAs (AdCL, SH, RE), pp. 916–921.

DAC-2007-Trimberger #design

Trusted Design in FPGAs (ST), pp. 5–8.

DAC-2007-ZhouTLW #how #logic

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs (CLZ, WCT, WHL, YLW), pp. 922–927.

DATE-2007-CuiDHG #2d #algorithm #configuration management #online #performance

An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs (JC, QD, XH, ZG), pp. 129–134.

PPoPP-2007-BondhugulaRS #automation

Automatic mapping of nested loops to FPGAS (UB, JR, PS), pp. 101–111.

DAC-2006-DupenloupLM #abstraction #functional #verification

Transistor abstraction for the functional verification of FPGAs (GD, TL, RM), pp. 1069–1072.

DAC-2006-MengSK #embedded #power management #reduction

Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.

DATE-2006-Heighton #design

Designing signal processing systems for FPGAs (JH), p. 92.

DATE-2006-KulkarniB #concurrent #framework #memory management #thread

Memory centric thread synchronization on platform FPGAs (CK, GJB), pp. 959–964.

DATE-2006-KumarA #power management

An analytical state dependent leakage power model for FPGAs (AK, MA), pp. 612–617.

DATE-2006-SethuramanV #architecture #automation #generative #multi #named #using

optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs (BS, RV), pp. 947–952.

DATE-2006-SutharD #detection #fault #multi #online #performance #testing

Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults (VS, SD), pp. 1165–1170.

DAC-2005-TomL #clustering #design #logic #scalability

Logic block clustering of large designs for channel-width constrained FPGAs (MT, GGL), pp. 726–731.

DATE-2005-GuoBNV #c #generative

Optimized Generation of Data-Path from C Codes for FPGAs (ZG, BB, WAN, KAV), pp. 112–117.

DATE-2005-HassanADE #power management #process #reduction

Activity Packing in FPGAs for Leakage Power Reduction (HH, MA, AED, MIE), pp. 212–217.

DATE-2005-KastensmidtSCR #composition #design #logic #on the

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.

DATE-2005-KeezerGMT #low cost #multi #using

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL (DCK, CG, AMM, NT), pp. 152–157.

DATE-2005-RodriguesC #compilation #design #framework

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs (RR, JMPC), pp. 30–31.

DAC-2004-MittalZTB #automation

Automatic translation of software binaries onto FPGAs (GM, DZ, XT, PB), pp. 389–394.

DAC-2004-OhbaT #design #embedded #using

An SoC design methodology using FPGAs and embedded microprocessors (NO, KT), pp. 747–752.

DAC-2004-SelvakkumaranRRK #algorithm #clustering #multi

Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources (NS, AR, SR, GK), pp. 741–746.

DAC-2004-VermaDS #online #performance #testing

Efficient on-line testing of FPGAs with provable diagnosabilities (VV, SD, VS), pp. 498–503.

DATE-DF-2004-PanatoSWJRB #design #multi #pipes and filters

Design of Very Deep Pipelined Multipliers for FPGAs (AP, SVS, FRW, MOJ, RR, SB), pp. 52–57.

DATE-v1-2004-Fit-FloreaHK #reliability

Enhancing Reliability of Operational Interconnections in FPGAs (AFF, MH, FK), pp. 746–747.

DATE-v2-2004-Krupnova #experience #industrial #multi

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience (HK), pp. 1236–1243.

DATE-v2-2004-KumarBK #algorithm #analysis #array #embedded #memory management #named #reduction #using

MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis (AMK, JB, VK), pp. 922–929.

DATE-v2-2004-TiwariT #embedded #finite #memory management #state machine

Saving Power by Mapping Finite-State Machines into Embedded Memory Blocks in FPGAs (AT, KAT), pp. 916–921.

DAC-2003-LimaCR #design #fault tolerance

Designing fault tolerant systems into SRAM-based FPGAs (FL, LC, RAdLR), pp. 650–655.

DAC-2003-MaideeAB #clustering #performance

Fast timing-driven partitioning-based placement for island style FPGAs (PM, CA, KB), pp. 598–603.

DAC-2003-MemikMJK #data flow #graph #resource management #synthesis

Global resource sharing for synthesis of control data flow graphs on FPGAs (SOM, GM, RJ, EK), pp. 604–609.

DAC-2003-RanM

Crosstalk noise in FPGAs (YR, MMS), pp. 944–949.

DATE-2003-BlodgetML #approach #configuration management #embedded #lightweight

A Lightweight Approach for Embedded Reconfiguration of FPGAs (BB, SM, PL), pp. 10399–10401.

DATE-2003-MoraesMPMC #configuration management #development

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs (FGM, DM, JCSP, LM, NLVC), pp. 11122–11123.

DATE-2003-SeidlEJ #using

Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information (US, KE, FMJ), pp. 10770–10777.

DAC-2002-AbramoviciSE #embedded #using

Using embedded FPGAs for SoC yield improvement (MA, CES, ME), pp. 713–724.

DAC-2002-KannanBB #estimation #metric #on the

On metrics for comparing routability estimation methods for FPGAs (PK, SB, DB), pp. 70–75.

DAC-2002-WirthlinM #using

IP delivery for FPGAs using Applets and JHDL (MJW, BM), pp. 2–7.

DATE-2002-AbkeB #automaton #implementation

A Direct Mapping System for Datapath Module and FSM Implementation into LUT-Based FPGAs (JA, EB), p. 1085.

DATE-2002-GericotaASF #concurrent #configuration management #novel

A Novel Methodology for the Concurrent Test of Partial and Dynamically Reconfigurable SRAM-Based FPGAs (MGG, GRA, MLS, JMF), p. 1126.

DATE-2002-NayakHCB

Accurate Area and Delay Estimators for FPGAs (AN, MH, ANC, PB), pp. 862–869.

ICPR-v3-2002-DraperBBRC #image #implementation

Implementing Image Applications on FPGAs (BAD, JRB, APWB, CR, MC), pp. 265–268.

DAC-2001-FanLWC #2d #design #on the

On Optimum Switch Box Designs for 2-D FPGAs (HF, JL, YLW, CCC), pp. 203–208.

DATE-2001-NamSR #approach #incremental #satisfiability

A boolean satisfiability-based incremental rerouting approach with application to FPGAs (GJN, KAS, RAR), pp. 560–565.

DATE-2001-NayakHCB #analysis #automation #fault #hardware #matlab #precise #synthesis

Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.

DAC-2000-ChangC #architecture #metric

An architecture-driven metric for simultaneous placement and global routing for FPGAs (YWC, YTC), pp. 567–572.

DATE-2000-KumthekarS #logic #optimisation #reduction

Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs (BK, FS), pp. 202–207.

DAC-1999-CongHX #performance

Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.

DATE-1999-KrupnovaS #clustering #multi

Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs (HK, GS), p. 587–?.

DAC-1998-CongX

Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (JC, SX), pp. 704–707.

DAC-1998-KumthekarBMS #optimisation

In-Place Power Optimization for LUT-Based FPGAs (BK, LB, EM, FS), pp. 718–721.

DATE-1998-MetraRMPPFZSS #novel #testing

Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.

DAC-1995-LeeW #performance

A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.

DAC-1995-SawkarT #clustering #multi

Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs (PS, DET), pp. 201–205.

DAC-1994-ChangCWM #layout #logic #synthesis

Layout Driven Logic Synthesis for FPGAs (SCC, KTC, NSW, MMS), pp. 308–313.

DAC-1994-KuznarBZ #clustering #multi

Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.

DAC-1994-NagR

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs (SN, RAR), pp. 301–307.

DAC-1994-ZhuW #bound

Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs (KZ, DFW), pp. 165–170.

DAC-1993-Mehendale #design #evaluation #independence #logic #named

MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs (MM), pp. 219–223.

DAC-1993-NagR #performance

Iterative Wirability and Performance Improvement for FPGAs (SN, KR), pp. 321–325.

DAC-1993-SawkarT #performance

Performance Directed Technology Mapping for Look-Up Table Based FPGAs (PS, DET), pp. 208–212.

DAC-1992-Palczewski #parallel

Plane Parallel a Maze Router and Its Application to FPGAs (MP), pp. 691–697.

DAC-1991-FrancisRV #named #performance

Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs (RJF, JR, ZGV), pp. 227–233.