BibSLEIGH — Prithviraj

Travelled to:

1 × Japan
1 × Poland
13 × USA
2 × Germany
5 × France

Collaborated with:

P.G.Joisha J.H.Patel R.Kling A.N.Choudhary S.Patil S.Roy G.Hasteer A.Mathur H.Zhou X.Tang R.Nevatia S.Roy N.D.Liveris A.Nayak M.Haldar V.Kim V.Chickermane R.J.Brouwer J.S.Sargent M.Jones D.R.Chakrabarti H.Boehm R.S.Schreiber U.N.Shenoy K.P.Belkhale M.Wang M.Sarrafzadeh H.Arts S.Parkes A.Mallik D.Sinha G.Mittal D.Zaretsky E.M.Rudnick S.Kim

Talks about:

algorithm (9) parallel (7) placement (6) power (6) optim (6) base (5) synthesi (4) standard (4) matlab (4) design (4)

Person: Prithviraj Banerjee

DBLP: Banerjee:Prithviraj

Contributed to:

2012

2011

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1994

1993

1992

1991

1990

1989

1987

Wrote 29 papers:

ICPR-2012-BanerjeeN #kernel #learning #multi #process #recognition #using: Pose based activity recognition using Multiple Kernel learning (PB, RN), pp. 445–448.
CGO-2011-ChakrabartiBBJS #graph #memory management #optimisation #runtime #transaction: The runtime abort graph and its application to software transactional memory optimization (DRC, PB, HJB, PGJ, RSS), pp. 42–53.
POPL-2011-JoishaSBBC #automation #compilation #effectiveness #optimisation #parallel #reuse #thread #using: A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code (PGJ, RSS, PB, HJB, DRC), pp. 623–636.
DATE-2006-MallikSBZ #design #optimisation #power management: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment (AM, DS, PB, HZ), pp. 618–623.
DAC-2005-TangZB #library #optimisation #power management #synthesis: Leakage power optimization with dual-Vth library in high-level synthesis (XT, HZ, PB), pp. 202–207.
DAC-2004-MittalZTB #automation: Automatic translation of software binaries onto FPGAs (GM, DZ, XT, PB), pp. 389–394.
DAC-2004-RoyB #algorithm #design #fixpoint #float #matlab: An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design (SR, PB), pp. 484–487.
DATE-v2-2004-LiverisB #design #interface #power management #synthesis: Power Aware Interface Synthesis for Bus-Based SoC Design (NDL, PB), pp. 864–869.
CC-2003-JoishaB #matlab #type inference: The MAGICA Type Inference Engine for MATLAB (PGJ, PB), pp. 121–125.
PLDI-2003-JoishaB #array #matlab #optimisation: Static array storage optimization in MATLAB (PGJ, PB), pp. 258–268.
DATE-2002-NayakHCB: Accurate Area and Delay Estimators for FPGAs (AN, MH, ANC, PB), pp. 862–869.
DATE-2001-NayakHCB #analysis #automation #fault #hardware #matlab #precise #synthesis: Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs (AN, MH, ANC, PB), pp. 722–728.
DATE-2000-ShenoyBC #algorithm #quality #synthesis: A System-Level Synthesis Algorithm with Guaranteed Solution Quality (UNS, PB, ANC), pp. 417–424.
DAC-1999-RoyBB #algorithm #constraints: An Approxmimate Algorithm for Delay-Constraint Technology Mapping (SR, KPB, PB), pp. 367–372.
DAC-1998-HasteerMB #algorithm #automaton #verification: An Implicit Algorithm for Finding Steady States and its Application to FSM Verification (GH, AM, PB), pp. 611–614.
DAC-1998-KimB #algorithm #estimation #parallel: Parallel Algorithms for Power Estimation (VK, PB), pp. 672–677.
DAC-1998-WangBS #named #semistructured data: Potential-NRG: Placement with Incomplete Data (MW, PB, MS), pp. 279–282.
DATE-1998-RoyAB #clustering #named #power management: PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions (SR, HA, PB), pp. 967–968.
DAC-1997-HasteerMB #performance: An Efficient Assertion Checker for Combinational Properties (GH, AM, PB), pp. 734–739.
DAC-1994-ParkesBP #approach #generative #named #object-oriented #parallel #testing: ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation (SP, PB, JHP), pp. 717–721.
DAC-1993-ChickermaneRBP: Non-Scan Design-for-Testability Techniques for Sequential Circuits (VC, EMR, PB, JHP), pp. 236–241.
DAC-1992-KimBCP #algorithm #named: APT: An Area-Performance-Testability Driven Placement Algorithm (SK, PB, VC, JHP), pp. 141–146.
DAC-1991-PatilBP #generative #parallel #testing: Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors (SP, PB, JHP), pp. 155–159.
DAC-1990-BrouwerB #named #parallel: PHIGURE: A Parallel Hierarchical Global Router (RJB, PB), pp. 650–653.
DAC-1990-KlingB #evolution #optimisation #standard: Optimization by Simulated Evolution with Applications to Standard Cell Placement (RMK, PB), pp. 20–25.
DAC-1989-PatilB #algorithm #bound #branch #generative #parallel #testing: A Parallel Branch and Bound Algorithm for Test Generation (SP, PB), pp. 339–343.
DAC-1989-SargentB #algorithm #fault #parallel #standard: A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control (JSS, PB), pp. 590–593.
DAC-1987-JonesB #algorithm #parallel #performance #standard: Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube (MJ, PB), pp. 807–813.
DAC-1987-KlingB #evolution #named #standard #using: ESP: A New Standard Cell Placement Package Using Simulated Evolution (RMK, PB), pp. 60–66.