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Travelled to:
1 × France
2 × USA
Collaborated with:
H.K.Kapoor D.P.Furey J.T.Udding
Talks about:
synthesi (2) insensit (2) specif (2) delay (2) asynchron (1) interfac (1) decompos (1) conflict (1) concurr (1) circuit (1)

Person: Mark B. Josephs

DBLP DBLP: Josephs:Mark_B=

Contributed to:

DAC 20042004
DATE 20002000
CAV 19901990

Wrote 3 papers:

DAC-2004-KapoorJ #concurrent #logic #specification #synthesis
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis (HKK, MBJ), pp. 830–833.
DATE-2000-JosephsF #interface #specification #synthesis
Delay-Insensitive Interface Specification and Synthesis (MBJ, DPF), pp. 169–173.
CAV-1990-JosephsU #algebra
An Algebra for Delay-Insensitive Circuits (MBJ, JTU), pp. 343–352.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.