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Travelled to:
1 × Germany
1 × USA
Collaborated with:
R.Zafalon C.Guardiani L.Navoni R.Canegallo G.Gozzini A.Kramer P.L.Rolandi
Talks about:
recognit (1) parallel (1) circuit (1) tempor (1) spatio (1) partit (1) memori (1) associ (1) simul (1) power (1)

Person: Mauro Chinosi

DBLP DBLP: Chinosi:Mauro

Contributed to:

DAC 19991999
ICDAR 19971997

Wrote 2 papers:

DAC-1999-ChinosiZG #clustering #parallel #simulation
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (MC, RZ, CG), pp. 562–567.
ICDAR-1997-NavoniCCGKR #memory management #recognition #using #word
Words Recognition using Associative Memory (LN, RC, MC, GG, AK, PLR), pp. 97–101.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.