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Travelled to:
3 × Germany
3 × USA
5 × France
Collaborated with:
V.Zaccaria M.Sami D.Sciuto C.Silvano A.Bona E.Macii G.Coppola O.Vermesan M.Chinosi C.Guardiani A.Macii F.Crudo M.Loghi F.Angiolini D.Bertozzi L.Benini M.Mazzillo P.G.Fallica E.Ficarra A.Messina M.Romeo M.Pedram D.Friebel R.C.Aitken A.Domic L.Salvemini
Talks about:
power (5) embed (5) vliw (4) processor (3) energi (3) level (3) methodolog (2) instruct (2) industri (2) system (2)

Person: Roberto Zafalon

DBLP DBLP: Zafalon:Roberto

Contributed to:

DATE 20132013
DATE 20112011
DATE 20062006
DATE DF 20042004
DATE v2 20042004
DATE 20032003
SAC 20032003
DAC 20022002
DATE 20022002
DATE 20012001
DAC 19991999

Wrote 11 papers:

DATE-2013-ZafalonCV #industrial
e-Mobility the next frontier for automotive industry (RZ, GC, OV), pp. 1745–1748.
DATE-2011-MazzilloFFMRZ #detection
Solid state photodetectors for nuclear medical imaging applications (MM, PGF, EF, AM, MR, RZ), pp. 511–512.
DATE-2006-MaciiPFADZ #design #matter #power management #question #tool support
Low-power design tools: are EDA vendors taking this matter seriously? (EM, MP, DF, RCA, AD, RZ), p. 1227.
DATE-DF-2004-BonaZZ #industrial #modelling #simulation
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip (AB, VZ, RZ), pp. 318–323.
DATE-v2-2004-LoghiABBZ #communication
Analyzing On-Chip Communication in a MPSoC Environment (ML, FA, DB, LB, RZ), pp. 752–757.
DATE-2003-MaciiMCZ #algorithm #embedded #energy
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.
SAC-2003-SalveminiSSSZZ #architecture #embedded #energy #performance #trade-off
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems (LS, MS, DS, CS, VZ, RZ), pp. 672–678.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation
Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2001-SamiSSZZ #embedded
Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.
DAC-1999-ChinosiZG #clustering #parallel #simulation
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (MC, RZ, CG), pp. 562–567.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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