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Travelled to:
1 × USA
Collaborated with:
J.Velamala R.LiVolsi Y.Cao
Talks about:
transient (1) circuit (1) sensit (1) design (1) singl (1) scale (1) logic (1) event (1)

Person: Myra Torres

DBLP DBLP: Torres:Myra

Contributed to:

DAC 20112011

Wrote 1 papers:

DAC-2011-VelamalaLTC #design #logic
Design sensitivity of single event transients in scaled logic circuits (JV, RL, MT, YC), pp. 694–699.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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