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Travelled to:
1 × Germany
2 × USA
Collaborated with:
Y.Cao R.LiVolsi M.Torres S.Chellappa J.Ni X.Yao N.D.Hindman M.Chen L.T.Clark E.Mintarno J.Skaf R.Zheng S.P.Boyd R.W.Dutton S.Mitra
Talks about:
circuit (2) transient (1) character (1) variabl (1) extract (1) sensit (1) design (1) singl (1) scale (1) optim (1)

Person: Jyothi Velamala

DBLP DBLP: Velamala:Jyothi

Contributed to:

DAC 20112011
DAC 20102010
DATE 20102010

Wrote 3 papers:

DAC-2011-VelamalaLTC #design #logic
Design sensitivity of single event transients in scaled logic circuits (JV, RL, MT, YC), pp. 694–699.
DAC-2010-ChellappaNYHVCCC #variability
In-situ characterization and extraction of SRAM variability (SC, JN, XY, NDH, JV, MC, YC, LTC), pp. 711–716.
DATE-2010-MintarnoSZVCBDM #self
Optimized self-tuning for circuit aging (EM, JS, RZ, JV, YC, SPB, RWD, SM), pp. 586–591.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.