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Travelled to:
1 × Germany
1 × Switzerland
Collaborated with:
A.Sen
Talks about:
voltag (2) island (2) effici (2) constraint (1) floorplan (1) techniqu (1) perspect (1) system (1) energi (1) design (1)

Person: Pavel Ghosh

DBLP DBLP: Ghosh:Pavel

Contributed to:

DATE 20102010
SAC 20102010

Wrote 2 papers:

DATE-2010-GhoshS #performance #perspective
Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PG, AS), pp. 654–657.
SAC-2010-GhoshS #constraints #design #energy #performance
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints (PG, AS), pp. 535–541.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.