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Travelled to:
1 × France
3 × USA
Collaborated with:
M.Abramovici H.Ajuha W.Ke D.T.Miller Y.H.Levendel S.G.Chappell J.F.Pellegrin A.M.Schowe
Talks about:
simul (3) delay (2) substitut (1) synthesi (1) function (1) segment (1) circuit (1) verifi (1) system (1) reduct (1)

Person: Premachandran R. Menon

DBLP DBLP: Menon:Premachandran_R=

Contributed to:

DAC 19831983
DAC 19821982
DAC 19761976

Wrote 5 papers:

EDAC-1994-AjuhaM #reduction
Delay Reduction by Segment Substitution (HA, PRM), pp. 82–86.
EDAC-1994-KeM #synthesis
Synthesis of Delay-Verifiable Two-Level Circuits (WK, PRM), pp. 297–301.
DAC-1983-AbramoviciMM #fault #simulation
Critical path tracing — an alternative to fault simulation (MA, PRM, DTM), pp. 214–220.
DAC-1982-AbramoviciLM #logic #simulation
A logic simulation machine (MA, YHL, PRM), pp. 65–73.
DAC-1976-ChappellMPS #functional #simulation
Functional simulation in the lamp system (SGC, PRM, JFP, AMS), pp. 42–47.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.