BibSLEIGH — Proceedings of the 20th Design Automation Conference

Charles E. Radke
Proceedings of the 20th Design Automation Conference
DAC, 1983.

SYS

@proceedings{DAC-1983,
	acmid         = "800032",
	address       = "Miami Beach, Florida, USA",
	editor        = "Charles E. Radke",
	isbn          = "0-8186-0026-8",
	publisher     = "{ACM/IEEE}",
	title         = "{Proceedings of the 20th Design Automation Conference}",
	year          = 1983,
}

Contents (130 items)

DAC-1983-Mayo #automation #challenge #design #lessons learnt: Design automation — lessons of the past, challenges for the future (JSM), pp. 1–2.
DAC-1983-Camoin #perspective: Central DA and its role: An executive view (RJC), p. 3.
DAC-1983-Hahn #design #multi: Computer Design Language — Version Munich (CDLM) a modern multi-level language (WH), pp. 4–11.
DAC-1983-RobinsonD #hardware: Programmimg languages for hardware description (PR, JD), pp. 12–16.
DAC-1983-LieberherrK #hardware #named: Zeus: A hardware description language for VLSI (KJL, SEK), pp. 17–23.
DAC-1983-Pawlak #modelling: Microprocessor systems modeling with MODLAN (AP), p. 24.
DAC-1983-KatzW #concept: Chip assemblers: Concepts and capabilities (RHK, SW), pp. 25–30.
DAC-1983-RosenbergBDDPPRW #design: A vertically integrated VLSI design environment (JBR, DGB, JAD, SWD, CJP, JP, CDR, NW), pp. 31–38.
DAC-1983-AhdootAC #design: IBM FSD VLSI chip design methodology (KA, RRA, LC), pp. 39–45.
DAC-1983-EliasW #compilation #design: The IC Module Compiler, a VLSI system design aid (NJE, AWW), pp. 46–49.
DAC-1983-ChiangV #detection #fault #logic #network #on the: On fault detection in CMOS logic networks (KWC, ZGV), pp. 50–56.
DAC-1983-SomenziGMP #testing #verification: A new integrated system for PLA testing and verification (FS, SG, MM, PP), pp. 57–63.
DAC-1983-JainA #generative #testing #using: Test generation for MOS circuits using D-algorithm (SKJ, VDA), pp. 64–70.
DAC-1983-OgiharaMTKF #bidirectional #design #generative #testing: Test generation for scan design circuits with tri-state modules and bidirectional terminals (TO, SM, YT, KK, HF), pp. 71–78.
DAC-1983-Sapiro #question #tool support: Engineering Workstations: Tools or toys? (SS), pp. 79–80.
DAC-1983-BoardM #architecture #evaluation #interactive #parallel #simulation: An interactive simulation facility for the evaluation of shared-resource architectures (Parallel ARchitecture SIMulator — PARSIM) (JABJ, PNM), pp. 83–92.
DAC-1983-SangsterM #logic #named #simulation: Aquarius: Logic simulation on an Engineering Workstation (AS, JM), pp. 93–99.
DAC-1983-StevensA #logic #multi: BIMOS, an MOS oriented multi-level logic simulator (PS, GA), pp. 100–106.
DAC-1983-LiaoW #algorithm #constraints #layout: An algorithm to compact a VLSI symbolic layout with mixed constraints (YZL, CKW), pp. 107–112.
DAC-1983-KedemW #layout: Graph-optimization techniques for IC layout and compaction (GK, HW), pp. 113–120.
DAC-1983-Schiele: Improved compaction by minimized length of wires (WLS), pp. 121–127.
DAC-1983-Prasad #named #tutorial: Tutorial — Group Technology (HRP), p. 128.
DAC-1983-Day #automation #re-engineering: Computer Aided Software Engineering (CASE) (FWD), pp. 129–136.
DAC-1983-LeathO #architecture #implementation: Software architecture for the implementation of a Computer-Aided Engineering system (CLL, SJO), pp. 137–142.
DAC-1983-KramlichBCH #development #visualisation: Program visualization: Graphics support for software development (DK, GPB, RTC, CFH), pp. 143–149.
DAC-1983-SasakiKOT #hardware #logic #named: HAL: A block level HArdware Logic simulator (TS, NK, KO, KT), pp. 150–156.
DAC-1983-BarzilaiHSTW #logic #simulation #using: Simulating pass transistor circuits using logic simulation machines (ZB, LMH, GMS, DTT, LSW), pp. 157–163.
DAC-1983-SupowitS #algorithm: Placement algorithms for custom VLSI (KJS, EAS), pp. 164–170.
DAC-1983-IosupoviczKB: A module interchange placement machine (AI, CK, MAB), pp. 171–174.
DAC-1983-KozawaTIHMOKYO #algorithm #automation: Automatic placement algorithms for high packing density V L S I (TK, HT, TI, MH, CM, YO, KK, NY, YO), pp. 175–181.
DAC-1983-ChyanB #algorithm #array: A placement algorithm for array processors (DJC, MAB), pp. 182–188.
DAC-1983-Frome: Incorporating the human factor in color CAD systems (FSF), pp. 189–195.
DAC-1983-Tendolkar: Diagnosis of TCM failures in the IBM 3081 Processor complex (NNT), pp. 196–200.
DAC-1983-Vida-TorkuR #fault #multi #quality: Quality level and fault coverage for multichip modules (EKVT, CER), pp. 201–206.
DAC-1983-LaiS #functional #testing: Functional testing of digital systems (KWL, DPS), pp. 207–213.
DAC-1983-AbramoviciMM #fault #simulation: Critical path tracing — an alternative to fault simulation (MA, PRM, DTM), pp. 214–220.
DAC-1983-UmrigarP #design #hardware #realtime #verification: Formal verification of a real-time hardware design (ZDU, VP), pp. 221–227.
DAC-1983-Wojcik #design #verification: Formal design verification of digital systems (ASW), pp. 228–234.
DAC-1983-Dunn #design #overview #verification: An overview of the design and verification subsystem of the Engineering Design System (LND), pp. 237–238.
DAC-1983-RubinH #design #logic: A logic design front-end for improved engineering productivity (FR, PWH), pp. 239–245.
DAC-1983-RimkusWCM #design #verification: Structured design verification: Function and timing (CJR, MRW, DDC, FJM), pp. 246–252.
DAC-1983-Bendas #design: Design through transformation (JBB), pp. 253–256.
DAC-1983-RothermelM #design #using: Routing method for VLSI design using irregular cells (HJR, DAM), pp. 257–262.
DAC-1983-Supowit #layout #standard: Reducing channel density in standard cell layout (KJS), pp. 263–269.
DAC-1983-MayoO #layout: Pictures with parentheses: Combining graphics and procedures in a VLSI layout tool (RNM, JKO), pp. 270–276.
DAC-1983-Warner #independence #industrial: Importance of device independence to the CADCAM industry (JRW), pp. 277–278.
DAC-1983-OkazakiMY #multi: A multiple media delay simulator for MOS LSI circuits (KO, TM, TY), pp. 279–285.
DAC-1983-KozakBG #array #design #simulation: Design aids for the simulation of bipolar gate arrays (PK, AKB, AG), pp. 286–292.
DAC-1983-Ramachandran: An improved switch-level simulator for MOS circuits (VR), pp. 293–299.
DAC-1983-Bhavsar #algorithm #calculus #design: Design For Test Calculus: An algorithm for DFT rules checking (DKB), pp. 300–307.
DAC-1983-BenmehrezM #implementation #performance: Measured performance of a programmed implementation of the subscripted D-Algorithm (CB, JFM), pp. 308–315.
DAC-1983-Paulson #testing: Classes of diagnostic tests (CP), pp. 316–322.
DAC-1983-Vida-TorkuH #generative #heuristic #petri net #testing: Petri Net based search directing heuristics for test generation (EKVT, BMH), pp. 323–330.
DAC-1983-HofmannL #approach #feature model #named: HEX: An instruction-driven approach to feature extraction (MH, UL), pp. 331–336.
DAC-1983-TarolliH: Hierarchical circuit extraction with detailed parasitic capacitance (GMT, WJH), pp. 337–345.
DAC-1983-BastianEFHM #simulation #specification: Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (JDB, ME, PJF, CEH, LPM), pp. 346–352.
DAC-1983-Barke #layout #verification: A layout verification system for analog bipolar integrated circuits (EB), pp. 353–359.
DAC-1983-TokumasuKOYN #geometry #modelling: Solid model in geometric modelling system: HICAD (ST, YK, YO, SY, NN), pp. 360–366.
DAC-1983-LeeF #database #integration #modelling: Integration of solid modeling and data base management for CAD/CAM (YCL, KSF), pp. 367–373.
DAC-1983-SequinS: UNIGRAFIX (CHS, PSS), pp. 374–381.
DAC-1983-BouyatBV #design #development #named: VERDI: A computer aided design system for development and city planning (MB, HB, JCV), pp. 382–385.
DAC-1983-Heilweil: Technology rules- the other side of technology dependent code (MFH), p. 389.
DAC-1983-Smith #independence #layout: Technology-independent circuit layout (RJSI), pp. 390–393.
DAC-1983-Reinke #design #perspective: Technology design rules — a user’s perspective (TRR), p. 394.
DAC-1983-Ehr #automation #design: Position paper role of technology design rules in Design Automation (GJVE), p. 395.
DAC-1983-ShellyT #statistics #verification: Statistical techniques of timing verification (JHS, DRT), pp. 396–402.
DAC-1983-TamuraON #analysis #layout: Path delay analysis for hierarchical building block layout system (ET, KO, TN), pp. 403–410.
DAC-1983-Jouppi #analysis: Timing analysis for nMOS VLSI (NPJ), pp. 411–418.
DAC-1983-GranackiP #design #performance #trade-off: The effect of register-transfer design tradeoffs on chip area and performance (JJG, ACP), pp. 419–424.
DAC-1983-SmithNBSW #array #automation #geometry #layout #named: VGAUA: The Variable Geometry Automated Universal Array layout System (DCS, RN, FB, SSS, JCW), pp. 425–429.
DAC-1983-StebniskyMWPF #automation #named #synthesis: APSS: An automatic PLA synthesis system (MWS, MJM, JCW, RP, AF), pp. 430–435.
DAC-1983-TervonenLM #design #documentation: Integrated computer aided design, documentation and manufacturing system for PCB electronics (MT, HL, TM), pp. 436–443.
DAC-1983-Litke: Minimizing PWB NC drilling (JDL), pp. 444–447.
DAC-1983-Drier #programming: Simplification of CNC programming for PWB routing (JD), p. 448.
DAC-1983-OdawaraIK #clustering: Partitioning and placement technique for bus-structured PWB (GO, KI, TK), pp. 449–456.
DAC-1983-Kang #linear: Linear ordering and application to placement (SK), pp. 457–464.
DAC-1983-FukunagaYSK #approach #graph #using: Placement of circuit modules using a graph space approach (KF, SY, HSS, TK), pp. 465–471.
DAC-1983-McFarland #behaviour #clustering #hardware: Computer-aided partitioning of behavioral hardware descriptions (MCM), pp. 472–478.
DAC-1983-KowalskiT #automation #design #prototype #type system: The VLSI Design Automation Assistant: Prototype system (TJK, DET), pp. 479–483.
DAC-1983-HitchcockT #automation #synthesis: A method of automatic data path synthesis (CYHI, DET), pp. 484–489.
DAC-1983-TsengS #automation #named #synthesis: Facet: A procedure for the automated synthesis of digital systems (CJT, DPS), pp. 490–496.
DAC-1983-RoseOP: N.mPc: A retrospective (CWR, GO, FIP), pp. 497–505.
DAC-1983-Druian #design #functional #modelling: Functional models for VLSI design (RLD), pp. 506–514.
DAC-1983-ChengGKW #development #functional #simulation: Functional simulation shortens the development cycle of a new computer (RC, BG, KK, JW), pp. 515–519.
DAC-1983-OrdyR: The N.2 System (GO, CWR), pp. 520–526.
DAC-1983-Bassett #programming: Computer Aided Programming (PB), pp. 527–529.
DAC-1983-MicheliS #array #logic #multi #named #programmable: PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays (GDM, ALSV), pp. 530–537.
DAC-1983-LiuA #bound: Bounds on the saved area ratio due to PLA folding (WL, DEA), pp. 538–544.
DAC-1983-Martinez-CarballidoP #named #reduction: PRONTO: Quick PLA product reduction (JMC, VMP), pp. 545–552.
DAC-1983-HuK #array #logic #programmable #reduction: Optimum reduction of programmable logic array (TCH, YSK), pp. 553–558.
DAC-1983-CohoonS #heuristic #problem: Heuristics for the Circuit Realization Problem (JC, SS), pp. 560–566.
DAC-1983-MetosO #diagrams #implementation #physics: Binary Decision Diagrams: From abstract representations to physical implementations (JSM, JVO), pp. 567–570.
DAC-1983-NattrassO #design: Some Computer Aided Engineering System design principles (HLN, GKO), pp. 571–577.
DAC-1983-Hsu #algorithm: General river routing algorithm (CPH), pp. 578–583.
DAC-1983-LeongL #problem: A new channel routing problem (HWL, CLL), pp. 584–590.
DAC-1983-BursteinP: Hierarchical channel router (MB, RNP), pp. 591–597.
DAC-1983-Haynie #automation #design #named #relational #tutorial: Tutorial: The relational data model for Design Automation (MNH), pp. 599–607.
DAC-1983-Hill #interface #visual notation: Edisim and Edicap: Graphical simulator interfaces (DDH), pp. 608–614.
DAC-1983-FlakeMM #algebra #logic #simulation: An algebra for logic strength simulation (PF, PM, GM), pp. 615–618.
DAC-1983-LoNB #data type: A data structure for MOS circuits (CYL, HNN, AKB), pp. 619–624.
DAC-1983-Dewey #development #hardware: VHSIC hardware description (VHDL) development program (AD), pp. 625–628.
DAC-1983-GriersonCRHKKMMN #array #collaboration #design #development: The UK5000 — successful collaborative development of an integrated design system for a 5000 gate CMOS array with built-in test (JRG, BC, DR, REH, HK, JCK, JAM, JMM, CON), pp. 629–636.
DAC-1983-KirkCSBT #array: Placement of irregular circuit elements on non-uniform gate arrays (HK, PDC, JAS, JDB, GLT), pp. 637–643.
DAC-1983-PrazicB #array #automation #using: Automatic routing of double layer gate arrays using a moving cursor (BDP, MAB), pp. 644–650.
DAC-1983-NewtonY #array #optimisation: Optimisation of global routing for the UK5000 gate array by iteration (CON, PAY), pp. 651–657.
DAC-1983-Robinson #array #automation #layout: Automatic layout for gate arrays with one layer of metal (PR0), pp. 658–664.
DAC-1983-Krohn #array: An over-cell gate array channel router (HEK), pp. 665–670.
DAC-1983-GamalS #array #statistics: A new statistical model for gate array routing (AEG, ZAS), pp. 671–674.
DAC-1983-Jennings #automation: A topology for semicustom array-structured LSI devices, and their automatic customisation (PJ), pp. 675–681.
DAC-1983-DalCero #automation #multi: Automatic batch processing in multilayer ceramic metallization (ND), pp. 682–685.
DAC-1983-Simon #named: CAD/CAM — the foundation for Computer Integrated Manufacturing (RLS), pp. 686–700.
DAC-1983-JainS: Test strategy for microprocessers (SKJ, AKS), pp. 703–708.
DAC-1983-Ulrich #concurrent #design #simulation #verification: A design verification methodology based on concurrent simulation and clock suppression (EU), pp. 709–712.
DAC-1983-LaPaughL #testing: Total stuct-at-fault testing by circuit transformation (ASL, RJL), pp. 713–716.
DAC-1983-Acken #fault #testing: Testing for bridging faults (shorts) in CMOS circuits (JMA), pp. 717–718.
DAC-1983-JordanP #interactive #logic #named: ILS — interactive logic simulator (GDJ, BBP), pp. 719–720.
DAC-1983-Gupta #named: ACE: A Circuit Extractor (AG), pp. 721–725.
DAC-1983-TsukizoeSKF: MACH : a high-hitting pattern checker for VLSI mask data (AT, JS, TK, HF), pp. 726–731.
DAC-1983-ChangA #consistency: Consistency checking for MOS/VLSI circuits (NSC, RA), pp. 732–733.
DAC-1983-SzymanskiW #algorithm #analysis #performance: Space efficient algorithms for VLSI artwork analysis (TGS, CJVW), pp. 734–739.
DAC-1983-McGarityS: Experiments with the SLIM Circuit Compactor (RM, DPS), pp. 740–746.
DAC-1983-Leblond #named: CAF: A computer-assisted floorplanning tool (AL), pp. 747–753.
DAC-1983-Moulton: Laying the power and ground wires on a VLSI chip (ASM), pp. 754–755.
DAC-1983-WyleczukMB #industrial: The Transfer of University Software for Industry Use (RW, LM, GB), pp. 756–761.
DAC-1983-BatiniC #concept #database #design #visual notation: A graphical tool for conceptual design of data base applications (CB, CC), pp. 762–773.
DAC-1983-Tomkinson #automation #design #named #tool support: UCAD: Building Design Automation with general purpose software tools on UNIX (JHT), pp. 774–787.
DAC-1983-WalkerT #behaviour: Behavioral level transformation in the CMU-DA system (RAW, DET), pp. 788–789.
DAC-1983-WimerS #optimisation #synthesis: HOPLA-PLA optimization and synthesis (SW, NS), pp. 790–794.
DAC-1983-Chuquillanqui #problem #scalability: Internal connection problem in large optimized PLAs (SC), pp. 795–802.
DAC-1983-Pawlak83a #modelling: Microprocessor systems modeling with MODLAN (AP), pp. 804–811.

Charles E. RadkeProceedings of the 20th Design Automation ConferenceDAC, 1983.

Contents (130 items)

Charles E. Radke
Proceedings of the 20th Design Automation Conference
DAC, 1983.