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Travelled to:
1 × Germany
12 × USA
Collaborated with:
M.A.Breuer D.T.Miller P.R.Menon E.M.Rudnick P.S.Parikh C.E.Stroud M.Emmert X.Yu J.T.d.Sousa D.G.Saab M.A.Iyer D.E.Long K.B.Rajan Y.H.Levendel K.Kumar Y.Santoso M.C.Merten P.Bradley K.N.Dwarakanath P.Levin G.Memmi D.Miller A.Nahir A.Ziv R.Galivanche A.J.Hu A.Camilleri B.Bentley H.Foster V.Bertacco S.Kapoor
Talks about:
sequenti (3) simul (3) fault (3) test (3) use (3) reconfigur (2) approach (2) silicon (2) freez (2) clock (2)

Person: Miron Abramovici

DBLP DBLP: Abramovici:Miron

Contributed to:

DAC 20102010
DAC 20062006
DAC 20022002
DAC 19991999
DATE 19991999
DAC 19961996
DAC 19931993
DAC 19921992
DAC 19831983
DAC 19821982
DAC 19811981
DAC 19801980
DAC 19771977

Wrote 14 papers:

DAC-2010-NahirZGHACBFBK #validation #verification
Bridging pre-silicon verification and post-silicon validation (AN, AZ, RG, AJH, MA, AC, BB, HF, VB, SK), pp. 94–95.
DAC-2006-AbramoviciBDLMM #configuration management #framework
A reconfigurable design-for-debug infrastructure for SoCs (MA, PB, KND, PL, GM, DM), pp. 7–12.
DAC-2002-AbramoviciSE #embedded #using
Using embedded FPGAs for SoC yield improvement (MA, CES, ME), pp. 713–724.
DAC-2002-AbramoviciYR #low cost
Low-cost sequential ATPG with clock-control DFT (MA, XY, EMR), pp. 243–248.
DAC-1999-AbramoviciSS #configuration management #hardware #satisfiability #using
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware (MA, JTdS, DGS), pp. 684–690.
DATE-1999-SantosoMRA #generative #named #testing #using
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy (YS, MCM, EMR, MA), p. 747–?.
DAC-1996-IyerLA #identification
Identifying Sequential Redundancies Without Search (MAI, DEL, MA), pp. 457–462.
DAC-1993-ParikhA #approach #cost analysis
A Cost-Based Approach to Partial Scan (PSP, MA), pp. 255–259.
DAC-1992-AbramoviciRM #approach #exclamation #testing
Freeze!: A New Approach for Testing Sequential Circuits (MA, KBR, DTM), pp. 22–25.
DAC-1983-AbramoviciMM #fault #simulation
Critical path tracing — an alternative to fault simulation (MA, PRM, DTM), pp. 214–220.
DAC-1982-AbramoviciLM #logic #simulation
A logic simulation machine (MA, YHL, PRM), pp. 65–73.
DAC-1981-Abramovici #algorithm #testing
A maximal resolution guided-probe testing algorithm (MA), pp. 189–195.
DAC-1980-AbramoviciB #analysis #fault
Fault diagnosis based on effect-cause analysis: An introduction (MA, MAB), pp. 69–76.
DAC-1977-AbramoviciBK #concurrent #fault #functional #modelling #simulation
Concurrent fault simulation and functional level modeling (MA, MAB, KK), pp. 128–137.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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