Proceedings of the 19th Design Automation Conference
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter

James S. Crabbe, Charles E. Radke, Hillel Ofek
Proceedings of the 19th Design Automation Conference
DAC, 1982.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DAC-1982,
	acmid         = "800263",
	address       = "Las Vegas, Nevada, USA",
	editor        = "James S. Crabbe and Charles E. Radke and Hillel Ofek",
	publisher     = "{ACM/IEEE}",
	title         = "{Proceedings of the 19th Design Automation Conference}",
	year          = 1982,
}

Contents (130 items)

DAC-1982-Breuer #automation #design #overview #state of the art
A survey of the state-of-the-art of design automation an invited presentation (MAB), p. 1.
DAC-1982-Marcotte #automation #named
Robotics: The new automation tool (HRM), pp. 2–8.
DAC-1982-Williams #design #testing
Design for testability (TWW), p. 9.
DAC-1982-ONeill #automation #design #re-engineering
A retrospective on software engineering in design automation (LAO), pp. 10–14.
DAC-1982-FriendensonBT #delivery #design #tool support
Designer’s Workbench: Delivery of cad tools (RAF, JRB, TJT), pp. 15–22.
DAC-1982-Thompson #approach
A utilitarian approach to CAD (TJT), pp. 23–29.
DAC-1982-CiesielskiK
An analytical method for compacting routing area in integrated circuits (MJC, EK), pp. 30–37.
DAC-1982-RaghavanS
Optimal single row router (RR, SS), pp. 38–45.
DAC-1982-Hsu #2d #algorithm
A new two-dimensional routing algorithm (CPH), pp. 46–50.
DAC-1982-Pfister #simulation
The Yorktown Simulation Engine: Introduction (GFP), pp. 51–54.
DAC-1982-Denneau #simulation
The Yorktown Simulation Engine (MD), pp. 55–59.
DAC-1982-KronstadtP #simulation
Software support for the Yorktown Simulation Engine (EK, GFP), pp. 60–64.
DAC-1982-AbramoviciLM #logic #simulation
A logic simulation machine (MA, YHL, PRM), pp. 65–73.
DAC-1982-Collins #overview
IBM 3081 system overview and technology (CAC), pp. 75–82.
DAC-1982-Monachino #design #scalability #verification
Design verification system for large-scale LSI designs (MM), pp. 83–90.
DAC-1982-Woodward #aspect-oriented #automation #design
Operational aspects of design automation for the IBM 3081 (RFW), pp. 91–95.
DAC-1982-FreundG #automation #design
Automated conversion of design data for building the IBM 3081 (VJFJ, JAG), pp. 96–103.
DAC-1982-Supowit #algorithm
A minimum-impact routing algorithm (KJS), pp. 104–112.
DAC-1982-Heyns #algorithm
The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layers (WH), pp. 113–120.
DAC-1982-TeraiKSY #layout
A consideration of the number of horizontal grids used in the routing of a masterslice layout (MT, HK, KS, TY), pp. 121–128.
DAC-1982-LieH #layout
A bus router for IC layout (ML, CSH), pp. 129–132.
DAC-1982-Grass #algorithm #bound
A depth-first branch-and-bound algorithm for optimal PLA folding (WG), pp. 133–140.
DAC-1982-EganL
Optimal bipartite folding of PLA (JRE, CLL), pp. 141–146.
DAC-1982-HachtelNS #array #logic #programmable
Techniques for programmable logic array folding (GDH, ARN, ALSV), pp. 147–155.
DAC-1982-TeelW #design #logic
A logic minimizer for VLSI PLA design (BT, DW), pp. 156–162.
DAC-1982-DonzeSJS #design
Philo-a VLSI design system (RLD, JS, MJ, GS), pp. 163–169.
DAC-1982-KangKL #adaptation #cpu #design #evolution #layout #logic #matrix #random
Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design (SMK, RHK, HFSL), pp. 170–174.
DAC-1982-FiducciaM #heuristic #linear #network
A linear-time heuristic for improving network partitions (CMF, RMM), pp. 175–181.
DAC-1982-PayneC #automation #clustering
Automated partitioning of hierarchically specified digital systems (TSP, WMvC), pp. 182–192.
DAC-1982-MaisselO #approach #design #documentation #hardware #interactive #simulation #synthesis
Interactive design language: A unified approach to hardware simulation, synthesis and documentation (LIM, DLO), pp. 193–201.
DAC-1982-PilotyB
The conlan project: Status and future plans (RP, DB), pp. 202–212.
DAC-1982-Rawlings
VHSIC HDL (JBR), p. 213.
DAC-1982-Sanborn #database #design #evolution
Evolution of the engineering design system data base (JLS), pp. 214–218.
DAC-1982-DammGK #automation #hardware
Hardware support for automatic routing (ED, HG, KK), pp. 219–223.
DAC-1982-NairHLV
Global wiring on a wire routing machine (RN, SJH, SL, RV), pp. 224–231.
DAC-1982-Seiler #architecture #design #hardware
A hardware assisted design rule check architecture (LS), pp. 232–238.
DAC-1982-ArbabLM #towards
Toward CAM-oriented CAD (FA, LL, MAM), pp. 239–245.
DAC-1982-InoueAF #design #layout #precise
A layout system for high precision design of progressive die (KI, MA, TF), pp. 246–252.
DAC-1982-HellerSM #design
The planar package planner for system designers (WRH, GBS, KM), pp. 253–260.
DAC-1982-Otten #automation #design
Automatic floorplan design (RHJMO), pp. 261–267.
DAC-1982-Bennett #database #design
A database management system for design engineers (JB), pp. 268–273.
DAC-1982-Katz #approach #database #design
A database approach for managing VLSI design data (RHK), pp. 274–282.
DAC-1982-SmithW #data transformation #design #low cost
A low cost, transportable, data management system for LSI/VLSI design (DCS, BSW), pp. 283–290.
DAC-1982-LarsenLS #equation #logic
Aw expanded logic equation list for checkout (RPL, JAL, AKS), pp. 291–299.
DAC-1982-ChuquillanquiS #named #optimisation #scalability
PAOLA: A tool for topological optimization of large PLAS (SC, TPS), pp. 300–306.
DAC-1982-LuhukayK #layout #synthesis
A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.
DAC-1982-DesMaraisSW #functional #modelling #simulation
A functional level modelling language for digital simulation (PJD, ESYS, PSW), pp. 315–320.
DAC-1982-ShivaC #composition #simulation #synthesis #using
Modular description/simulation/synthesis using DDL (SGS, JAC), pp. 321–329.
DAC-1982-TraceyK #hardware
A hardware description language for processor based digital systems (JHT, KSK), pp. 330–337.
DAC-1982-Bruggere #hardware
Special purpose vs. general purpose hardware for da (THB), p. 338.
DAC-1982-Adshead #algorithm #complexity #hardware #problem #question #scalability #towards
Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help? (HGA), pp. 339–344.
DAC-1982-TamminenS #data access #geometry #performance
The excell method for efficient geometric access to data (MT, RS), pp. 345–351.
DAC-1982-Kedem #algorithm #data type #online
The quad-CIF tree: A data structure for hierarchical on-line algorithms (GK), pp. 352–357.
DAC-1982-Grabel #data type #distributed #towards
Object data structures towards distributed graphics processing (DG), pp. 358–364.
DAC-1982-Szepieniec #assembly #named
SAGA: An Experimental Silicon Assembler (AAS), pp. 365–370.
DAC-1982-TrimbergerR #assembly #named #visual notation
Riot — a simple graphical chip assembly tool (ST, JAR), pp. 371–376.
DAC-1982-GrayBR #array #compilation #design #using
Designing gate arrays using a silicon compiler (JPG, IB, PSR), pp. 377–383.
DAC-1982-MinS #fault #functional #testing
Testing functional faults in VLSI (YM, SYHS), pp. 384–392.
DAC-1982-Hayes #fault #simulation
A fault simulation methodology for VLSI (JPH), pp. 393–399.
DAC-1982-BoseKLNPW #fault
A fault simulator for MOS LSI circuits (AKB, PK, CYL, HNN, EPS, KWW), pp. 400–409.
DAC-1982-LiptonN #algorithm #automation #design #research
Design automation algorithms: Research and applications (RJL, JDN), p. 410.
DAC-1982-Asano #parametricity
Parametric pattern router (TA), pp. 411–417.
DAC-1982-RivestF
A “greedy” channel router (RLR, CMF), pp. 418–424.
DAC-1982-Korn #performance
An efficient variable-cost maze router (RKK), pp. 425–431.
DAC-1982-DeesK #automation
Automated rip-up and reroute techniques (WADJ, PGK), pp. 432–439.
DAC-1982-Richardson
Important criteria in selecting engineering work stations (FR), pp. 440–444.
DAC-1982-Shliferstein #interactive #using
Experiments using interactive color raster graphics for CAD (ARS), pp. 445–452.
DAC-1982-Price #design
Design of command menus for CAD systems (LAP), pp. 453–459.
DAC-1982-KellerNE #design
A symbolic design system for integrated circuits (KHK, ARN, SE), pp. 460–466.
DAC-1982-LiptonNSVV #named
ALI: A procedural language to describe VLSI layouts (RJL, SCN, RS, JV, GV), pp. 467–474.
DAC-1982-Rivest
The “PI” (placement and interconnect) system (RLR), pp. 475–481.
DAC-1982-GoelM
Electronic Chip-in-Place Test (PG, MTM), pp. 482–488.
DAC-1982-Saluja #fault #generative
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage (KKS), pp. 489–494.
DAC-1982-McCluskey #testing #verification
Verification testing (EJM), pp. 495–500.
DAC-1982-Kalay #bound #modelling #multi #parametricity
Modeling polyhedral solids bounded by multi-curved parametric surfaces (YEK), pp. 501–507.
DAC-1982-Glass #architecture #case study #design #user interface
A user interface for architectural design, a case study (GJG), pp. 508–513.
DAC-1982-LiuE #design
Design of a graphic processor for computer-aided drafting (CKL, CME), pp. 514–520.
DAC-1982-CosmaiCMN #2d #interactive
An interactive drafting system based on two dimensional primitives (GC, UC, PM, AN), pp. 521–529.
DAC-1982-ArnoldO #approach #geometry #layout #named
Lyra: A new approach to geometric layout rule checking (MHA, JKO), pp. 530–536.
DAC-1982-MudgeRLA #image #layout #validation
Cellular image processing techniques for VLSI circuit layout validation and routing (TNM, RAR, RML, DEA), pp. 537–543.
DAC-1982-TakashimaMCY #source code #verification
Programs for verifying circuit connectivity of mos/lsi mask artwork (MT, TM, TC, KY), pp. 544–550.
DAC-1982-Kaplan #strict #verification
A “non-restrictive” artwork verification program for printed circuit boards (DK), pp. 551–558.
DAC-1982-AllenET #automation #interface #named
DORA: : CAD interface to automatic diagnostics (RWA, MMEW, RET), pp. 559–565.
DAC-1982-BellonLSSVGI #automation #generative #source code
Automatic generation of microprocessor test programs (CB, AL, SS, GS, RV, FG, MI), pp. 566–573.
DAC-1982-BoseA #array #generative #logic #programmable #testing
Test generation for programmable logic arrays (PB, JAA), pp. 574–580.
DAC-1982-GoelM82a #analysis #interactive #testing
An interactive testability analysis program — ITTAP (DKG, RMM), pp. 581–586.
DAC-1982-UlrichH #modelling #network #simulation
Speed and accuracy in digital network simulation based on structural modeling (EU, DH), pp. 587–593.
DAC-1982-Sr #analysis #verification
Timing Verification and the Timing Analysis program (RBHS), pp. 594–604.
DAC-1982-BeningLAS #analysis #logic #network
Developments in logic network path delay analysis (LB, TAL, CRA, JES), pp. 605–615.
DAC-1982-Putatunda #automation #named
Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips (RP), pp. 616–621.
DAC-1982-NomuraSTAY #verification
Timing verification system based on delay time hierarchical nature (MN, SS, NT, TA, AY), pp. 622–628.
DAC-1982-Agrawal #analysis
Synchronous path analysis in MOS circuit simulator (VDA), pp. 629–635.
DAC-1982-Peled #data type
Simplified data structure for “mini-based” turnkey CAD systems (JP), pp. 636–642.
DAC-1982-GingerichCCL #hybrid
A hybrid CAD/CAM system for mechanical applications (JZG, MPC, EJC, PKL), pp. 643–649.
DAC-1982-Robbins
Making the wire frame solid (DR), pp. 650–654.
DAC-1982-KambeCKION #algorithm #evaluation
A placement algorithm for polycell LSI and ITS evaluation (TK, TC, SK, TI, NO, IN), pp. 655–662.
DAC-1982-MalingMH #on the
On finding most optimal rectangular package plans (KM, SHM, WRH), pp. 663–670.
DAC-1982-WipflerWM #algorithm #layout
A combined force and cut algorithm for hierarchical VLSI layout (GJW, MW, DAM), pp. 671–677.
DAC-1982-McDermott #modelling
Transmission gate modeling in an existing three-value simulator (RMM), pp. 678–681.
DAC-1982-LelarasmeeS #named #scalability
Relax: A new circuit for large scale MOS integrated circuits (EL, ALSV), pp. 682–687.
DAC-1982-LightnerH #algorithm #functional #megamodelling #testing
Implication algorithms for MOS switch level functional macromodeling implication and testing (MRL, GDH), pp. 691–698.
DAC-1982-NoonRR #approach #design
A design system approach to data integrity (WAN, KNR, MTR), pp. 699–705.
DAC-1982-HongYL
QCADS-a LSI CAD system for minicomputer (XLH, RkY, XlL), pp. 706–711.
DAC-1982-EustaceM #approach #automaton #design #finite
A Deterministic finite automaton approach to design rule checking for VLSI (RAE, AM), pp. 712–717.
DAC-1982-OdawaraIK
Arbitrarily-sized module location technique in the lop system (GO, KI, TK), pp. 718–726.
DAC-1982-ShiraishiIKN #design #named
ICAD/PCB: Integrated computer aided design system for printed circuit boards (HS, MI, SK, MN), pp. 727–732.
DAC-1982-WieselM #2d #problem
Two-dimensional channel routing and channel intersection problems (MW, DAM), pp. 733–739.
DAC-1982-NestorT #design #implementation #multi #representation #simulation
Defining and implementing a multilevel design representation with simulation applications (JAN, DET), pp. 740–746.
DAC-1982-SakaiTYOOKKY #design #interactive #logic #simulation
An Interactive Simulation System for structured logic design — ISS (TS, YT, HY, YO, YO, HK, SK, SY), pp. 747–754.
DAC-1982-HirakawaSM #logic #simulation
Logic simulation for LSI (KH, NS, MM), pp. 755–761.
DAC-1982-Pawlak #logic #modelling
Digital logic modeling system based on MODLAN (AP), pp. 763–770.
DAC-1982-Gelman #editing
VEEP A VEctor Editor and Preparer (SJG), pp. 771–776.
DAC-1982-Hassett #approach #automation #layout #problem
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI (JEH), pp. 777–784.
DAC-1982-AdachiKNS #design #layout #top-down
Hierarchical top-down layout design method for VLSI chip (TA, HK, MN, TS), pp. 785–791.
DAC-1982-ToddHPBGAB #array #layout #multi
CGALA-a multi technology Gate Array Layout system (LFT, JMH, SVP, JLB, DJG, RJA, AKB), pp. 792–801.
DAC-1982-MatsudaFTMNKG #design #layout #low cost #named
LAMBDA: A quick, low cost layout design system for master-slice LSI s (TM, TF, KT, HM, HN, FK, SG), pp. 802–808.
DAC-1982-PitchumaniS #design #formal method #verification
A formal method for computer design verification (VP, EPS), pp. 809–814.
DAC-1982-MuellerV #automation #semantics
Formal semantics for the automated derivation of micro-code (RAM, JV), pp. 815–824.
DAC-1982-Leinwand #correctness #logic
Logical correctness by construction (SML), pp. 825–831.
DAC-1982-MaruyamaUKS #design #hardware #verification
A verification technique for hardware designs (FM, TU, NK, TS), pp. 832–841.
DAC-1982-Chu #design
Computer system design description (YC), pp. 842–850.
DAC-1982-BassetS #design #testing #top-down
Top down design and testability of VLSI circuits (PB, GS), pp. 851–857.
DAC-1982-KawatoUHS #interactive #logic #synthesis
An interactive logic synthesis system based upon AI techniques (NK, TU, SH, TS), pp. 858–864.
DAC-1982-Sparr #database
A language for a scientific and engineering database system (TMS), pp. 865–871.
DAC-1982-BeylsHLMP #design #layout #tool support
A design methodology based upon symbolic layout and integrated cad tools (AMB, BH, JL, GM, AP), pp. 872–878.
DAC-1982-ChandrasekharB
Optimum placement of two rectangular blocks (MSC, MAB), pp. 879–886.
DAC-1982-SyedGB #on the
On routing for custom integrated circuits (ZAS, AEG, MAB), pp. 887–893.
DAC-1982-Pinter #on the
On routing two-point nets across a channel (RYP), pp. 894–902.
DAC-1982-OusterhoutU #design #metric
Measurements of a VLSI design (JKO, DMU), pp. 903–908.
DAC-1982-Levy #design #distributed
Distributed computation for design aids (SYL), pp. 909–915.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.