BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Canada
1 × France
1 × Singapore
Collaborated with:
A.Gupta V.M.A.KiranKumar R.Nalumasu A.Mokkedem G.Gopalakrishnan R.Kaivola N.Narasimhan A.Telfer J.Whittemore S.Pandav A.Slobodová C.Taylor V.Frolov E.Reeber A.Naik
Talks about:
formal (3) verif (2) model (2) intel (2) test (2) multiprocessor (1) processor (1) approach (1) graphic (1) verifi (1)

Person: Rajnish Ghughal

DBLP DBLP: Ghughal:Rajnish

Contributed to:

FM 20142014
CAV 20092009
CAV 19981998

Wrote 3 papers:

FM-2014-GuptaKG #experience #verification
Formally Verifying Graphics FPU — An Intel® Experience (AG, VMAK, RG), pp. 673–687.
CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.
CAV-1998-NalumasuGMG #approach #memory management #model checking #modelling #multi #verification
The “Test Model-Checking” Approach to the Verification of Formal Memory Models of Multiprocessors (RN, RG, AM, GG), pp. 464–476.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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