Stem intel$ (all stems)

27 papers:

VLDB-2015-JhaHLCH #approach #in memory #memory management

Improving Main Memory Hash Joins on Intel Xeon Phi Processors: An Experimental Approach (SJ, BH, ML, XC, HPH), pp. 642–653.

CGO-2015-TangZLLHLG #multi #optimisation

Optimizing and auto-tuning scale-free sparse matrix-vector multiplication on Intel Xeon Phi (WTT, RZ, ML, YL, HPH, XL, RSMG), pp. 136–145.

CAV-2015-Leslie-HurdCF #verification

Verifying Linearizability of Intel® Software Guard Extensions (RLH, DC, MF), pp. 144–160.

DAC-2014-RaiHST #detection #fault #framework #performance #realtime

An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor (DR, PH, NS, LT), p. 6.

FM-2014-GuptaKG #experience #verification

Formally Verifying Graphics FPU — An Intel® Experience (AG, VMAK, RG), pp. 673–687.

HPCA-2014-KarnagelDRLLSL #database #in memory #performance #transaction

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions (TK, RD, RR, KL, TL, BS, WL), pp. 476–487.

HPDC-2014-RajachandrasekarPVHWP #architecture #distributed #framework #named

MIC-Check: a distributed check pointing framework for the intel many integrated cores architecture (RR, SP, AV, KH, MWuR, DKP), pp. 121–124.

DAC-2013-RaiSST #algorithm #analysis #distributed #network #process

Distributed stable states for process networks: algorithm, analysis, and experiments on intel SCC (DR, LS, NS, LT), p. 10.

EDOC-2011-CurleyK #case study #framework #maturity #using

Using the IT Capability Maturity Framework to Improve IT Capability and Value Creation: An Intel IT Case Study (MC, JK), pp. 107–115.

PADL-2011-Kaivola #execution #framework #functional #validation

Intel CoreTM i7 Processor Execution Engine Validation in a Functional Language Based Formal Framework (RK), p. 1.

CGO-2011-NewburnSLMGTWDCWGLZ #array #compilation #embedded

Intel’s Array Building Blocks: A retargetable, dynamic compiler and embedded language (CJN, BS, ZL, MDM, AMG, SDT, ZGW, ZD, YC, GW, PG, ZL, DZ), pp. 224–235.

CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification

Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.

DAC-2008-Beers #experience #verification

Pre-RTL formal verification: an intel experience (RB), pp. 806–811.

DAC-2008-MandalBMM #design #named #towards

IntellBatt: towards smarter battery design (SKM, PB, SPM, RNM), pp. 872–877.

HPCA-2008-Rattner

Intel’s Tera-scale Computing Project: The first five years, the next five years (JR), p. 1.

SAC-2006-ErshovNM #architecture #precise

Quad and correctly rounded double precision math functions: portable and optimized for Intel architectures (AE, AN, SM), pp. 1310–1317.

RE-2005-Nesland #framework #implementation #lessons learnt #process #requirements

Initial Lessons Learned from the Definition and Implementation of a Platform Requirements Engineering Process at Intel Corporation (SN), pp. 429–433.

CGO-2004-KimLWCTZWYGS #physics #thread

Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors (DK, SWL, PHW, JdC, XT, XZ, HW, DY, MG, JPS), pp. 27–38.

CGO-2004-LukMPCL #architecture #named

Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture (CKL, RM, HP, RSC, PGL), pp. 15–26.

LCTES-2004-ContrerasMPJL #named

XTREM: a power simulator for the Intel XScale® core (GC, MM, JP, RJ, GYL), pp. 115–125.

CGO-2003-CollardL #optimisation

Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor (JFC, DML), pp. 105–114.

CGO-2003-SettleCHL #architecture #optimisation #stack

Optimization for the Intel® Itanium ®Architectur Register Stack (AS, DAC, GH, DML), pp. 115–124.

LICS-2003-Harrison #verification

Formal Verification at Intel (JH), p. 45–?.

DAC-2001-Bentley #validation

Validating the Intel Pentium 4 Microprocessor (BB), pp. 244–248.

SAC-1997-Lee

Constructing the constrained Delaunay triangulation on the Intel paragon (FL), pp. 464–467.

DAC-1987-JonesB #algorithm #parallel #performance #standard

Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube (MJ, PB), pp. 807–813.

DAC-1984-Nachtsheim #automation #design

The Intel design automation system (SN), pp. 459–465.