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Travelled to:
2 × France
Collaborated with:
R.Kaivola R.Ghughal A.Telfer J.Whittemore S.Pandav A.Slobodová C.Taylor V.Frolov E.Reeber A.Naik
Talks about:
formal (2) verif (2) processor (1) multipli (1) pentium (1) replac (1) execut (1) valid (1) point (1) intel (1)

Person: Naren Narasimhan

DBLP DBLP: Narasimhan:Naren

Contributed to:

CAV 20092009
DATE 20022002

Wrote 2 papers:

CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification
Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.
DATE-2002-KaivolaN #float #multi #verification
Formal Verification of the Pentium ® 4 Floating-Point Multiplier (RK, NN), pp. 20–27.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.