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Travelled to:
1 × France
Collaborated with:
K.Schneider T.Kropf
Talks about:
hardwar (1) specif (1) formal (1) verif (1) vhdl (1)

Person: Ralf Reetz

DBLP DBLP: Reetz:Ralf

Contributed to:

DATE 19981998

Wrote 1 papers:

DATE-1998-ReetzSK #hardware #specification #verification
Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.