BibSLEIGH — Thomas

Travelled to:

1 × Denmark
1 × Portugal
1 × United Kingdom
3 × USA
5 × Germany
7 × France

Collaborated with:

J.Ruf K.Schneider W.Rosenstiel R.Kumar D.W.Hoffmann P.Heckeler ∅ J.Frößl O.F.Haberl D.Lettnin P.K.Nalla B.Schlich R.Reetz S.Huster S.Burg H.Eichelberger J.Behrend J.Gerlach M.Huhn G.Logothetis V.Schönknecht S.Reitemeyer H.Post C.Sinz F.Merz T.Gorges P.M.Peranandam R.J.Weiss W.Müller J.Laufenberg S.Lämmermann A.Viehl A.Jesser L.Hedrich T.Kirsten

Talks about:

verif (7) softwar (6) properti (4) circuit (4) base (4) hardwar (3) automot (3) simul (3) check (3) time (3)

Person: Thomas Kropf

DBLP: Kropf:Thomas

Contributed to:

2015

2014

2013

2011

2010

2009

2008

2007

2006

2001

2000

1999

1998

1997

1994

1992

1991

Wrote 22 papers:

SEFM-2015-HusterBELRKR #performance #testing: Efficient Testing of Different Loop Paths (SH, SB, HE, JL, JR, TK, WR), pp. 117–131.
SEFM-2014-HusterHERBKR #flexibility #invariant #specification: More Flexible Object Invariants with Less Specification Overhead (SH, PH, HE, JR, SB, TK, WR), pp. 302–316.
SAC-2013-HeckelerSK #component #execution #robust #testing #using: Accelerated robustness testing of state-based components using reverse execution (PH, BS, TK), pp. 1188–1195.
DATE-2011-BehrendLHRKR #embedded #hybrid #scalability #verification: Scalable hybrid verification for embedded software (JB, DL, PH, JR, TK, WR), pp. 179–184.
DATE-2010-LammermannRKRVJH #design #towards #verification: Towards assertion-based verification of heterogeneous system designs (SL, JR, TK, WR, AV, AJ, LH), pp. 1171–1176.
DATE-2009-LettninNBRGKRSR #hardware #verification: Semiformal verification of temporal properties in automotive hardware dependent software (DL, PKN, JB, JR, JG, TK, WR, VS, SR), pp. 1214–1217.
RE-2009-PostSMGK #functional #requirements #verification: Linking Functional Requirements and Software Verification (HP, CS, FM, TG, TK), pp. 295–302.
DATE-2008-LettninNRKRKSR #embedded #verification: Verification of Temporal Properties in Automotive Embedded Software (DL, PKN, JR, TK, WR, TK, VS, SR), pp. 164–169.
CAV-2007-Kropf #debugging #development #formal method #industrial #question: Software Bugs Seen from an Industrial Perspective or Can Formal Methods Help on Automotive Software Development? (TK), p. 3.
DAC-2006-PeranandamNRWKR #bound #performance: Fast falsification based on symbolic bounded property checking (PMP, PKN, JR, RJW, TK, WR), pp. 1077–1082.
DATE-2001-RufHGKRM #semantics #simulation: The simulation semantics of systemC (JR, DWH, JG, TK, WR, WM), pp. 64–70.
DATE-2001-RufHKR #multi: Simulation-guided property checking based on a multi-valued AR-automata (JR, DWH, TK, WR), pp. 742–748.
DATE-2000-HoffmannK #fault #multi: Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits (DWH, TK), p. 758.
DATE-2000-RufK #realtime: Analyzing Real-Time Systems (JR, TK), pp. 243–248.
DATE-1999-HuhnSKL #verification: Verifying Imprecisely Working Arithmetic Circuits (MH, KS, TK, GL), p. 65–?.
DATE-1998-ReetzSK #hardware #specification #verification: Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.
EDTC-1997-KropfR #model checking #using: Using MTBDDs for discrete timed symbolic model checking (TK, JR), pp. 182–187.
EDAC-1994-FrosslK #simulation: A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation (JF, TK), pp. 343–348.
EDAC-1994-HaberlK #interface #maintenance #standard: Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface (OFH, TK), pp. 220–225.
EDAC-1994-SchneiderKK #verification: Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path (KS, TK, RK), pp. 648–652.
CADE-1992-SchneiderKK #proving: The FAUST — Prover (KS, RK, TK), pp. 766–770.
CAV-1991-SchneiderKK #automation #hardware #proving: Automating Most Parts of Hardware Proofs in HOL (KS, RK, TK), pp. 365–375.