BibSLEIGH — Proceedings of the Third Conference on Design, Automation and Test in Europe

Proceedings of the Third Conference on Design, Automation and Test in Europe
DATE, 1998.

SYS

@proceedings{DATE-1998,
	address       = "Paris, France",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Third Conference on Design, Automation and Test in Europe}",
	year          = 1998,
}

Contents (172 items)

DATE-1998-ChatzigeorgiouN #effectiveness: Collapsing the Transistor Chain to an Effective Single Equivalent Transistor (AC, SN), pp. 2–6.
DATE-1998-NicolaidisD #design #multi #predict: Design of Fault-Secure Parity-Prediction Booth Multipliers (MN, RdOD), pp. 7–14.
DATE-1998-OgawaKK #memory management #named: PASTEL: A Parameterized Memory Characterization System (KO, MK, FK), pp. 15–20.
DATE-1998-GrodeKM #clustering #hardware #resource management: Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System (JG, PVK, JM), pp. 22–27.
DATE-1998-SrinivasanRV #clustering #design #hardware: Hardware Software Partitioning with Integrated Hardware Design Space Exploration (VS, SR, RV), pp. 28–35.
DATE-1998-GasteierGM #communication #generative #synthesis: Generation of Interconnect Topologies for Communication Synthesis (MG, MG, MM), pp. 36–42.
DATE-1998-TanFY #design: The Design of an Asynchronous VHDL Synthesizer (SYT, SBF, WFY), pp. 44–51.
DATE-1998-GrimmW #clustering #hybrid: Repartitioning and Technology-Mapping of Electronic Hybrid Systems (CG, KW), pp. 52–58.
DATE-1998-MoserM #design #modelling #named: VHDL-AMS: The Missing Link in System Design — Experiments with Unified Modelling in Automotive Engineering (EM, NM), pp. 59–63.
DATE-1998-ParulkarGB #scheduling: Scheduling and Module Assignment for Reducing Bist Resources (IP, SKG, MAB), pp. 66–73.
DATE-1998-YangP #algorithm #performance #scheduling #synthesis: An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis (LTY, ZP), pp. 74–81.
DATE-1998-RenovellPFZ #approach #configuration management #logic: RAM-Based FPGA’s: A Test Approach for the Configurable Logic (MR, JMP, JF, YZ), pp. 82–88.
DATE-1998-MetraRMPPFZSS #novel #testing: Novel Technique for Testing FPGAs (CM, MR, GAM, JMP, SP, JF, YZ, DS, GRS), pp. 89–94.
DATE-1998-DiazPC: ATM Traffic Shaper: ATS (JCD, PP, JC), pp. 96–101.
DATE-1998-LagoJLSB #fuzzy #logic #named #synthesis: XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers (EL, CJJ, DRL, SSS, ABB), pp. 102–107.
DATE-1998-EpplerFGM #energy #network #physics: High Speed Neural Network Chip for Trigger Purposes in High Energy Physics (WE, TF, HG, AM), pp. 108–115.
DATE-1998-DaveJ #architecture #concurrent #embedded #named #realtime #specification: CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures (BPD, NKJ), pp. 118–124.
DATE-1998-LeijtenMTJ #communication #multi #realtime: Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor (JAJL, JLvM, AHT, JAGJ), pp. 125–131.
DATE-1998-ElesKPDP #embedded #graph #process #scheduling #synthesis: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems (PE, KK, ZP, AD, PP), pp. 132–138.
DATE-1998-HsiehL #abstraction #verification: Model Abstraction for Formal Verification (YWH, SPL), pp. 140–147.
DATE-1998-CoppensAR #analysis #fault #modelling: VHDL Modelling and Analysis of Fault Secure Systems (JC, DAK, CR), pp. 148–152.
DATE-1998-Mutz #modelling: Register Transfer Level VHDL Models without Clocks (MM), pp. 153–158.
DATE-1998-Naroska #parallel #simulation: Parallel VHDL Simulation (EN), pp. 159–163.
DATE-1998-ZhaoP #self #source code #testing: Testing DSP Cores Based on Self-Test Programs (WZ, CAP), pp. 166–172.
DATE-1998-YarmolikHW #performance #self: Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs (VNY, SH, HJW), pp. 173–179.
DATE-1998-BogueGJZ #self: Built-In Self-Test with an Alternating Output (TB, MG, HJ, YZ), pp. 180–184.
DATE-1998-SchneiderKHD #algorithm #architecture #comparison #hardware: From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms (CS, MK, TH, JD), pp. 186–190.
DATE-1998-RassauYCLECW #2d #implementation #mobile #parallel: Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications (AMR, TCBY, HC, SL, KE, WAC, TDW), pp. 191–195.
DATE-1998-UrrizaAGBN #architecture #image #using: VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform (IU, JIA, JIGN, LAB, DN), pp. 196–201.
DATE-1998-AllaraFSS #analysis #profiling: A Model for System-Level Timed Analysis and Profiling (AA, WF, FS, DS), pp. 204–210.
DATE-1998-Lin #compilation #concurrent #performance #runtime #scheduling #source code: Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling (BL), pp. 211–217.
DATE-1998-MaestroMM #clustering #estimation #hardware #parallel #process: A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process (JAM, DM, HM), pp. 218–225.
DATE-1998-GerlachR #design #estimation #scalability: A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment (JG, WR), pp. 226–231.
DATE-1998-SchumacherN #hardware #modelling #object-oriented #parallel: Object-Oriented Modelling of Parallel Hardware Systems (GS, WN), pp. 234–241.
DATE-1998-Putzke-RomingRN #flexibility #message passing: A Flexible Message Passing Mechanism for Objective VHDL (WPR, MR, WN), pp. 242–249.
DATE-1998-Mrva #object-oriented #reuse: Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL (MM), pp. 250–256.
DATE-1998-ReetzSK #hardware #specification #verification: Formal Specification in VHDL for Hardware Verification (RR, KS, TK), pp. 257–263.
DATE-1998-AntolaPS #approach #detection #fault: A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths (AA, VP, MS), pp. 266–272.
DATE-1998-WangAZ #array #design #effectiveness #validation: Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays (LCW, MSA, JZ), pp. 273–277.
DATE-1998-ChangCML #functional #testing: Functional Scan Chain Testing (DC, KTC, MMS, MTCL), pp. 278–283.
DATE-1998-Martin #design: Design Methodologies for System Level IP (GM), pp. 286–289.
DATE-1998-Loore #design: IP-Based System-on-a-Chip Design (BdL), p. 290.
DATE-1998-KoegstGCW #analysis #design #reuse: A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits (MK, DG, PC, MGW), pp. 292–296.
DATE-1998-OlcozAIP: VHDL Teamwork, Organization Units and Workspace Management (SO, LA, II, OP), pp. 297–302.
DATE-1998-BottgerAMS #implementation #object-oriented #prototype #reuse #specification: An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse (JB, KA, DM, SS), pp. 303–310.
DATE-1998-KoehlBLKP #design: A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.
DATE-1998-Vygen #algorithm #standard: Algorithms for Detailed Placement of Standard Cells (JV), pp. 321–324.
DATE-1998-FassnachtS #analysis #optimisation: Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset (UF, JS), pp. 325–331.
DATE-1998-Hetzel #graph #grid: A Sequential Detailed Router for Huge Grid Graphs (AH), pp. 332–338.
DATE-1998-Neely #configuration management #logic: Reconfigurable Logic for Systems on a Chip (WSN), p. 340.
DATE-1998-RabaeyW #configuration management #energy: An Energy-Conscious Exploration Methodology for Reconfigurable DSPs (JMR, MW), pp. 341–342.
DATE-1998-Page #design: Design Of Future Systems (IP), pp. 343–347.
DATE-1998-ChandramouliWS #analysis #functional #named: AFTA: A Formal Delay Model for Functional Timing Analysis (VC, JW, KAS), pp. 350–355.
DATE-1998-RabeJKNO #performance #trade-off: Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs (DR, GJ, LK, WN), pp. 356–361.
DATE-1998-SchmerlerTM #logic #simulation: Advanced Optimistic Approaches in Logic Simulation (SS, YT, KDMG), pp. 362–368.
DATE-1998-PyttelSV #architecture #named #parallel #scalability: PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems (AP, AS, CV), pp. 370–376.
DATE-1998-MesmanSTMJ #approach #constraints #pipes and filters: A Constraint Driven Approach to Loop Pipelining and Register Binding (BM, MTJS, AHT, JLvM, JAGJ), pp. 377–383.
DATE-1998-YiCPHK #behaviour #multi #synthesis: Multiple Behavior Module Synthesis Based on Selective Groupings (JHY, HC, ICP, SHH, CMK), pp. 384–388.
DATE-1998-KaulV #architecture #clustering #configuration management #synthesis: Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures (MK, RV), pp. 389–396.
DATE-1998-SongSZ #clustering #concept #effectiveness: An Effective General Connectivity Concept for Clustering (JS, ZS, WZ), pp. 398–405.
DATE-1998-HelvigRZ #approximate #bound #problem: Improved Approximation Bounds for the Group Steiner Problem (CSH, GR, AZ), pp. 406–413.
DATE-1998-AdlerS #design #interactive: An Interactive Router for Analog IC Design (TA, JS), pp. 414–420.
DATE-1998-Rosenstiel #design #industrial #standard #verification: Formal Verification: A New Standard CAD Tool for the Industrial Design Flow (WR), p. 422.
DATE-1998-PostMG #design #hardware: A System-Level Co-Verification Environment for ATM Hardware Design (GP, AM, TG), pp. 424–428.
DATE-1998-KedingWCM #design #fixpoint #named #simulation: FRIDGE: A Fixed-Point Design and Simulation Environment (HK, MW, MC, HM), pp. 429–435.
DATE-1998-HansenKR #comparison #interface #simulation #synthesis #using #verification: Verification by Simulation Comparison using Interface Synthesis (CH, AK, WR), pp. 436–443.
DATE-1998-XuK #architecture #synthesis: Layout-Driven High Level Synthesis for FPGA Based Architectures (MX, FJK), pp. 446–450.
DATE-1998-BringmannR #synthesis: Cross-Level Hierarchical High-Level Synthesis (OB, WR), pp. 451–456.
DATE-1998-LiG #algorithm #behaviour: An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions (JL, RKG), pp. 457–463.
DATE-1998-WangK #reduction: A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction (DW, ESK), pp. 466–470.
DATE-1998-KahngMSS: Interconnect Tuning Strategies for High-Performance Ics (ABK, SM, ES, RS), pp. 471–478.
DATE-1998-ChuW #algorithm #polynomial: A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing (CCNC, DFW), pp. 479–485.
DATE-1998-Rosenstiel98a #design #generative #tool support: Next Generation System Level Design Tools (WR), p. 488–?.
DATE-1998-Rodriguez-MontanesF #estimation: Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs (RRM, JF), pp. 490–494.
DATE-1998-StrakaMVS #metric: A Fully Digital Controlled Off-Chip IDDQ Measurement Unit (BS, HARM, JV, MS), pp. 495–500.
DATE-1998-GoorT #testing: March Tests for Word-Oriented Memories (AJvdG, IBST), pp. 501–508.
DATE-1998-NeulBLSHW #approach #component #modelling #simulation: A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation (RN, UB, GL, PS, JH, SW), pp. 510–517.
DATE-1998-SzekelyR #performance #static analysis: Fast Field Solvers for Thermal and Electrostatic Analysis (VS, MR), pp. 518–523.
DATE-1998-LubaszewskiCC #approach #problem #testing: Microsystems Testing: an Approach and Open Problems (ML, ÉFC, BC), pp. 524–528.
DATE-1998-FreundF #approximate #linear #modelling #multi #scalability #using: Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation (RWF, PF), pp. 530–537.
DATE-1998-MarquesKWS #3d #algorithm #modelling #order #performance #reduction: An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models (NAM, MK, JW, LMS), pp. 538–543.
DATE-1998-ShaoC #approximate #design #using: MCM Interconnect Design Using Two-Pole Approximation (JS, RMMC), pp. 544–548.
DATE-1998-MalyNHK #interface: Design-Manufacturing Interface: Part I — Vision (WM, PKN, HTH, JK), pp. 550–556.
DATE-1998-MalyNOHKS #interface: Design-Manufacturing Interface: Part II — Applications (WM, PKN, CHO, HTH, JK, PS), pp. 557–562.
DATE-1998-HeinekenM #design #named #performance #trade-off: Performance — Manufacturability Tradeoffs in IC Design (HTH, WM), pp. 563–567.
DATE-1998-RudnickVECPR #generative #performance #testing #using: Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques (EMR, RV, AE, FC, PP, MSR), pp. 570–576.
DATE-1998-HsiaoC #performance #sequence: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits (MSH, STC), pp. 577–582.
DATE-1998-GuoPR #sequence #testing: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration (RG, IP, SMR), pp. 583–587.
DATE-1998-JemaiKJ #architecture #behaviour #simulation #synthesis: Architectural Simulation in the Context of Behavioral Synthesis (AJ, PK, AAJ), pp. 590–595.
DATE-1998-ObergHK #communication #grammarware #hardware #protocol #scheduling #synthesis: Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols (JÖ, AH, AK), pp. 596–603.
DATE-1998-HamiltonO #concurrent #fault #latency: Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs (SNH, AO), pp. 604–609.
DATE-1998-HorethD #diagrams: Dynamic Minimization of Word-Level Decision Diagrams (SH, RD), pp. 612–617.
DATE-1998-Eijk #equivalence #traversal: Sequential Equivalence Checking without State Space Traversal (CAJvE), pp. 618–623.
DATE-1998-RibasC #equivalence #incremental #on the #reuse #simulation #verification: On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits (LR, JC), pp. 624–629.
DATE-1998-DoorselaerNRM #debugging: Silicon Debug of Systems-on-Chips (KvD, SN, GJvR, EJM), pp. 632–633.
DATE-1998-EckmuellerGG: Hierarchical Characterization of Analog Integrated CMOS Circuits (JE, MG, HEG), pp. 636–643.
DATE-1998-DroegeTH #named: EASY — a System for Computer-Aided Examination of Analog Circuits (GD, MT, EHH), pp. 644–648.
DATE-1998-HedrichB #approach #formal method #linear #parametricity #verification: A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances (LH, EB), pp. 649–654.
DATE-1998-GhoshKBH #benchmark #equivalence #invariant #metric #synthesis: Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking (DG, NK, FB, JEHI), pp. 656–663.
DATE-1998-LuSJ: Technology Mapping for Minimizing Gate and Routing Area (AL, GS, FMJ), pp. 664–669.
DATE-1998-CornoPRV: Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection (FC, PP, MSR, MV), pp. 670–677.
DATE-1998-DagaOA: Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
DATE-1998-WangV #data-driven #optimisation: Data Driven Power Optimization of Sequential Circuits (QW, SBKV), pp. 686–691.
DATE-1998-OhP: Gated Clock Routing Minimizing the Switched Capacitance (JO, MP), pp. 692–697.
DATE-1998-JiangC #approximate #estimation: Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits (YMJ, KTC), pp. 698–702.
DATE-1998-WehnH #architecture #embedded #trade-off: Embedded DRAM Architectural Trade-Offs (NW, SH), pp. 704–708.
DATE-1998-Catthoor #architecture #design #energy #performance: Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions (FC), pp. 709–714.
DATE-1998-VandenbusscheDLGS #design #interface #specification #top-down: Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon (JV, SD, FL, GGEG, WMCS), pp. 716–720.
DATE-1998-RosenbergerH #approach #behaviour #functional #modelling #simulation: A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks (RR, SAH), pp. 721–728.
DATE-1998-BisdounisKGN #modelling: Switching Response Modeling of the CMOS Inverter for Sub-micron Devices (LB, OGK, CEG, SN), pp. 729–735.
DATE-1998-Cheng #multi #on the: On Removing Multiple Redundancies in Combinational Circuits (DIC), pp. 738–742.
DATE-1998-Scholl #composition #functional #multi: Multi-output Functional Decomposition with Exploitation of Don’t Cares (CS), pp. 743–748.
DATE-1998-RuttenBEK #algorithm #divide and conquer #logic #performance: An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization (JWJMR, MRCMB, CAJvE, MAJK), pp. 749–754.
DATE-1998-SawadaYN #detection #logic: Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions (HS, SY, AN), pp. 755–759.
DATE-1998-FerrandiFMP #behaviour #estimation: Power Estimation of Behavioral Descriptions (FF, FF, EM, MP), pp. 762–766.
DATE-1998-BoglioloBM #behaviour #modelling: Characterization-Free Behavioral Power Modeling (AB, LB, GDM), pp. 767–773.
DATE-1998-MarculescuMP #estimation #probability: Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation (DM, RM, MP), pp. 774–779.
DATE-1998-VercauterenVJL #analysis #partial order #performance #using #verification: Efficient Verification using Generalized Partial Order Analysis (SV, DV, GGdJ, BL), pp. 782–789.
DATE-1998-PastorC #analysis #encoding #performance #petri net: Efficient Encoding Schemes for Symbolic Analysis of Petri Nets (EP, JC), pp. 790–795.
DATE-1998-KassabCAK #analysis #constraints: Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis (MK, EC, SA, THK), pp. 796–802.
DATE-1998-GoldbergKB #functional #specification #verification: Combinational Verification based on High-Level Functional Specifications (EIG, YK, RKB), pp. 803–808.
DATE-1998-MirRVH #analysis #fault: Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems (SM, AR, DV, JLH), pp. 810–814.
DATE-1998-RenovellAB #implementation #multi: Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits (MR, FA, YB), pp. 815–821.
DATE-1998-LindermeirVG #design #detection #fault #metric #parametricity: Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults (WML, TJV, HEG), pp. 822–827.
DATE-1998-Coudert #encoding #paradigm: A New Paradigm for Dichotomy-based Constrained Encoding (OC), pp. 830–834.
DATE-1998-MartinezAQH #problem: A Dynamic Model for the State Assignment Problem (MM, MJA, JMQ, JLH), pp. 835–839.
DATE-1998-MaheshwariS #performance #scalability: Efficient Minarea Retiming of Large Level-Clocked Circuits (NM, SSS), pp. 840–845.
DATE-1998-KhouriLJ #control flow #named #power management #synthesis: IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits (KSK, GL, NKJ), pp. 848–854.
DATE-1998-TomiyamaIIY #design #reduction #scheduling: Instruction Scheduling for Power Reduction in Processor-Based System Design (HT, TI, AI, HY), pp. 855–860.
DATE-1998-BeniniMSMS #encoding #optimisation: Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.
DATE-1998-MrvaBK #architecture #concurrent #java #multi #scalability #thread: A Scalable Architecture for Multi-threaded JAVA Applications (MM, KB, RK), pp. 868–874.
DATE-1998-SalapuraG #co-evolution #design #fuzzy #hardware: Hardware/Software Co-Design of a Fuzzy RISC Processor (VS, MG), pp. 875–882.
DATE-1998-HiguchiS #design: Innovative System-level Design Environment Based on FORM for Transport Processing System (KH, KS), pp. 883–890.
DATE-1998-CostaCS #modelling #performance #simulation: Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC’s (JPC, MC, LMS), pp. 892–898.
DATE-1998-TianS #fault #performance #simulation: Efficient DC Fault Simulation of Nonlinear Analog Circuits (MWT, CJRS), pp. 899–904.
DATE-1998-PrietoRGPHR #approach #design #fault #layout #predict #testing: An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits (JAP, AR, IAG, EJP, JLH, AMDR), pp. 905–909.
DATE-1998-NiemannM #communication #concurrent #hardware #synthesis: Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems (RN, PM), pp. 912–913.
DATE-1998-Lopez-VallejoIL #clustering #knowledge-based: A Knowledge-based System for Hardware-Software Partitioning (MLLV, CAI, JCL), pp. 914–915.
DATE-1998-Kazmierski: A Formal Description of VHDL-AMS Analogue Systems (TJK), pp. 916–920.
DATE-1998-FlottesPRV #effectiveness #performance: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique (MLF, RP, BR, LV), pp. 921–922.
DATE-1998-RunjeK #encryption #implementation: Universal Strong Encryption FPGA Core Implementation (DR, MK), pp. 923–924.
DATE-1998-PandaDN #embedded: Data Cache Sizing for Embedded Processor Applications (PRP, NDD, AN), pp. 925–926.
DATE-1998-CalvezHMP #generative #multi #programmable: A Programmable Multi-Language Generator for CoDesign (JPC, DH, FM, OP), pp. 927–928.
DATE-1998-BasuLM #source code: Register-Constrained Address Computation in DSP Programs (AB, RL, PM), pp. 929–930.
DATE-1998-Muller-WipperfurthH #modelling #visual notation: Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base (TMW, RH), pp. 931–932.
DATE-1998-EconomakosPT #attribute grammar #automation #design #grammarware #named: AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems (GE, GKP, PT), pp. 933–934.
DATE-1998-OlcozCGG #static analysis #tool support: Static Analysis Tools for Soft-Core Reviews and Audits (SO, AC, MG, JAG), pp. 935–936.
DATE-1998-WahlV #performance #validation: A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor (MGW, HV), pp. 937–938.
DATE-1998-MartinR: A Comparing Study of Technology Mapping for FPGA (HGM, WR), pp. 939–940.
DATE-1998-Kazmierski98a #interface #simulation: Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation (TJK), pp. 941–944.
DATE-1998-SungH #hardware: Optimized Timed Hardware Software Cosimulation without Roll-back (WS, SH), pp. 945–946.
DATE-1998-Montiel-NelsonASN #compilation #design: A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design (JAMN, VdA, RS, AN), pp. 947–948.
DATE-1998-GongCK #architecture #synthesis: Architectural Rule Checking for High-level Synthesis (JG, CTC, KK), pp. 949–950.
DATE-1998-KimuraI #analysis #design: A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator (HK, NI), pp. 951–952.
DATE-1998-NordholzGTONAW #testing: Core Interconnect Testing Hazards (PN, HG, DT, JO, DN, UA, TWW), pp. 953–954.
DATE-1998-RiesgoTTU #estimation #fault #functional #modelling #quality #validation: Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models (TR, YT, EdlT, JU), pp. 955–956.
DATE-1998-BolchiniSS #analysis #concurrent #detection #fault #network: Fault Analysis in Networks with Concurrent Error Detection Properties (CB, FS, DS), pp. 957–958.
DATE-1998-SvajdaSM #metric #named: IOCIMU — An Integrated Off-Chip IDDQ Measurement Unit (MS, BS, HARM), pp. 959–960.
DATE-1998-WolfK #automation #generative #optimisation: Automatic Topology Optimization for Analog Module Generators (MW, UK), pp. 961–962.
DATE-1998-Prihozhy #scheduling: Asynchronous Scheduling and Allocation (AP), pp. 963–964.
DATE-1998-RingeLB #satisfiability #using #verification: Path Verification Using Boolean Satisfiability (MR, TL, EB), pp. 965–966.
DATE-1998-RoyAB #clustering #named #power management: PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions (SR, HA, PB), pp. 967–968.
DATE-1998-RoethigZA #design #modelling: Power and Timing Modeling for ASIC Designs (WR, AMZ, MA), pp. 969–970.
DATE-1998-ArsintescuO #constraints #layout: Constraints Space Management for the Layout of Analog IC’s (BGA, RHJMO), pp. 971–972.
DATE-1998-PomeranzR #flexibility #logic #synthesis: A Synthesis Procedure for Flexible Logic Functions (IP, SMR), pp. 973–974.
DATE-1998-Nicoli #behaviour #semantics #set: Denotational Semantics of a Behavioral Subset of VHDL (FN), pp. 975–976.
DATE-1998-MendiasH #formal method #perspective #synthesis: Correct High-Level Synthesis: a Formal Perspective (JMM, RH), pp. 977–978.
DATE-1998-NouraniP #fault #testing: A Bypass Scheme for Core-Based System Fault Testing (MN, CAP), pp. 979–980.
DATE-1998-MetraFR: Highly Testable and Compact 1-out-of-n Code Checker with Single Output (CM, MF, BR), pp. 981–982.
DATE-1998-PomeranzR98a #using: Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines (IP, SMR), pp. 983–984.
DATE-1998-PullelaPDV: CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
DATE-1998-Velasco-MedinaCN #detection #fault #injection #linear #using: Fault Detection for Linear Analog Circuits Using Current Injection (JVM, TC, MN), pp. 987–988.

Proceedings of the Third Conference on Design, Automation and Test in EuropeDATE, 1998.

Contents (172 items)

Proceedings of the Third Conference on Design, Automation and Test in Europe
DATE, 1998.