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Travelled to:
1 × USA
Collaborated with:
N.Chou B.Salefski C.Cheng
Talks about:
synthesi (1) shortest (1) communic (1) steiner (1) system (1) power (1) graph (1) path (1) gate (1) chip (1)

Person: Renshen Wang

DBLP DBLP: Wang:Renshen

Contributed to:

DAC 20092009

Wrote 1 papers:

DAC-2009-WangCSC #graph #power management #synthesis #using
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.