BibSLEIGH — Chung-Kuan

Travelled to:

1 × Germany
18 × USA
2 × France

Collaborated with:

L.Liu M.Kuo X.Hong J.Lillis T.Y.Lin E.S.Kuh H.Peng J.Huang P.Guo T.Hamada P.M.Chau R.Shi N.Chou W.Yu Z.Qin F.Liu R.C.C.IV D.N.Deutsch B.Yao Z.Zhu H.Zhuang X.Hu P.Suaris T.Yoshimura J.Xu H.Liou M.Shih C.Yeh H.Chen Y.Ma S.Dong Y.Cai J.Gu Y.Zhu S.Weng J.Lin Z.Zhang N.Wong R.Wang B.Salefski C.J.Chang M.Marek-Sadowska Y.Pang F.Balasa K.Lampaert J.Li C.Ho T.C.Hu L.Zhang I.Kang X.Wang Y.Hu R.L.Graham W.Dai R.Lindelof T.Xue S.Yao D.Dutt S.Nahar C.Lo J.Lu P.Chen C.Chang L.Sha D.J.Huang C.Teng S.Chen A.S.Arani M.Popovich T.Toms X.Chen H.Zhu A.Deutsch G.A.Katopis D.M.Dreps A.B.Kahng J.F.MacDonald W.Zhang Z.Zhu L.Chua-Eoan R.Murgai T.Shibuya N.Ito

Talks about:

use (11) placement (7) network (7) power (7) algorithm (6) partit (6) effici (6) block (6) base (6) approach (5)

Person: Chung-Kuan Cheng

DBLP: Cheng:Chung=Kuan

Contributed to:

2015

2014

2011

2009

2008

2006

2003

2001

2000

1999

1998

1997

1996

1995

1994

1993

1992

1991

1988

Wrote 39 papers:

DAC-2015-ZhuangYKWC #algorithm #exponential #framework #performance #scalability #simulation #using: An algorithmic framework for efficient large-scale circuit simulation using exponential integrators (HZ, WY, IK, XW, CKC), p. 6.
DAC-2014-LuCCSHTC #named #using: ePlace: Electrostatics Based Placement Using Nesterov’s Method (JL, PC, CCC, LS, DJHH, CCT, CKC), p. 6.
DAC-2014-ZhuangWLC #distributed #framework #named #network #simulation: MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks (HZ, SHW, JHL, CKC), p. 6.
DATE-2011-ZhangHCW #grid #network #power management #reduction: A block-diagonal structured model reduction scheme for power grid networks (ZZ, XH, CKC, NW), pp. 44–49.
DAC-2009-WangCSC #graph #power management #synthesis #using: Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.
DATE-2009-AraniHPCYPTC #3d #reliability: Reliability aware through silicon via planning for 3D stacked ICs (ASA, XH, HP, CKC, WY, MP, TT, XC), pp. 288–291.
DATE-2009-PengC #parallel #simulation: Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.
DAC-2008-ZhangYZDKDKC #optimisation #power management #using: Low power passive equalizer optimization using tritonic step response (LZ, WY, HZ, AD, GAK, DMD, ESK, CKC), pp. 570–573.
DATE-2008-ZhangZYZSPZCMSIC #multi #network: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
DAC-2006-HuZCGC #communication #latency #power management #synthesis: Communication latency aware low power NoC synthesis (YH, YZ, HC, RLG, CKC), pp. 574–579.
DAC-2006-ShiC #array #performance: Efficient escape routing for hexagonal array of high density I/Os (RS, CKC), pp. 1003–1008.
DAC-2003-ChenCCKMSYZ #algebra #clustering #layout #multi: An algebraic multigrid solver for analytical placement with layout based clustering (HC, CKC, NCC, ABK, JFM, PS, BY, ZZ), pp. 794–799.
DAC-2003-MaHDCCCG #analysis #optimisation: Dynamic global buffer planning optimization based on detail block locating and congestion analysis (YM, XH, SD, SC, YC, CKC, JG), pp. 806–811.
DAC-2003-QinC #reduction #using: Realizable parasitic reduction using generalized Y-Delta transformation (ZQ, CKC), pp. 220–225.
DAC-2003-ZhuYC #adaptation #algebra #analysis #approach #multi #network #using: Power network analysis using an adaptive algebraic multigrid approach (ZZ, BY, CKC), pp. 105–108.
DAC-2001-MaHDCCG #constraints: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List (YM, XH, SD, YC, CKC, JG), pp. 770–775.
DAC-2000-ChangCSM #detection #functional #performance #symmetry #using: Fast post-placement rewiring using easily detectable functional symmetries (CWJC, CKC, PS, MMS), pp. 286–289.
DAC-2000-PangBLC #constraints #representation #symmetry: Block placement with symmetry constraints based on the O-tree non-slicing representation (YP, FB, KL, CKC), pp. 464–467.
DAC-1999-GuoCY #representation: An O-Tree Representation of Non-Slicing Floorplan and Its Applications (PNG, CKC, TY), pp. 268–273.
DAC-1998-LiuC: Extending Moment Computation to 2-Port Circuit Representations (FJL, CKC), pp. 473–476.
DAC-1997-KuoC #approach #clustering #network: A Network Flow Approach for Hierarchical Tree Partitioning (MTK, CKC), pp. 512–517.
DAC-1997-LillisC #multi #optimisation: Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion (JL, CKC), pp. 214–219.
DAC-1997-XuGC #clustering #refinement: Cluster Refinement for Block Placement (JX, PNG, CKC), pp. 762–765.
DAC-1996-KuoLC #clustering #network: Network Partitioning into Tree Hierarchies (MTK, LTL, CKC), pp. 477–482.
DAC-1996-LiLLC #approach #clustering #linear: New Spectral Linear Placement and Clustering Approach (JL, JL, LTL, CKC), pp. 88–93.
DAC-1996-LillisCLH #performance #trade-off: New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing (JL, CKC, TTYL, CYH), pp. 395–400.
DAC-1996-LiouLC #performance #pipes and filters #pseudo #testing: Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming (HYL, TTYL, CKC), pp. 274–279.
DAC-1995-LiuKCH #approach #clustering #graph #replication #using: Performance-Driven Partitioning Using a Replication Graph Approach (LTL, MTK, CKC, TCH), pp. 206–210.
DAC-1994-ChouLCDL #clustering #logic: Circuit Partitioning for Huge Logic Emulation Systems (NCC, LTL, CKC, WJD, RL), pp. 244–249.
DAC-1994-LiuSC #clustering #data flow #latency: Data Flow Partitioning for Clock Period and Latency Minimization (LTL, MS, CKC), pp. 658–663.
DAC-1993-HamadaCC #approach #linear #named #network #using: Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach (TH, CKC, PMC), pp. 531–536.
DAC-1993-HongXKCH #algorithm: Performance-Driven Steiner Tree Algorithm for Global Routing (XH, TX, ESK, CKC, JH), pp. 177–181.
DAC-1993-HuangHCK #algorithm #performance: An Efficient Timing-Driven Global Routing Algorithm (JH, XH, CKC, ESK), pp. 596–600.
DAC-1993-YaoCDNL #using: Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP (SZY, CKC, DD, SN, CYL), pp. 395–400.
DAC-1992-HamadaCC #equation #estimation: A Wire Length Estimation Technique Utilizing Neighborhood Density Equations (TH, CKC, PMC), pp. 57–61.
DAC-1992-HongHCK #algorithm #named #performance: FARM: An Efficient Feed-Through Pin Assignment Algorithm (XH, JH, CKC, ESK), pp. 530–535.
DAC-1991-CardenC #algorithm #approximate #multi #performance #using: A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm (RCCI, CKC), pp. 316–321.
DAC-1991-YehCL #algorithm #clustering #multi: A General Purpose Multiple Way Partitioning Algorithm (CWY, CKC, TTYL), pp. 421–426.
DAC-1988-ChengD: Improved Channel Routing by Via Minimization and Shifting (CKC, DND), pp. 677–680.