BibSLEIGH corpus
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Travelled to:
2 × France
Collaborated with:
A.Glebov V.Zolotov C.Oh R.Panda M.R.Becer S.Rusakov D.Blaauw L.G.Jones G.Vijayan
Talks about:
circuit (2) analysi (1) static (1) domino (1) calcul (1) power (1) digit (1) nois (1) loss (1) fast (1)

Person: Sergey Gavrilov

DBLP DBLP: Gavrilov:Sergey

Contributed to:

DATE v2 20042004
ED&TC 19971997

Wrote 2 papers:

DATE-v2-2004-GlebovGZOPB #analysis
False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
EDTC-1997-GavrilovGRBJV #performance
Fast power loss calculation for digital static CMOS circuits (SG, AG, SR, DB, LGJ, GV), pp. 411–415.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.