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Travelled to:
1 × Germany
3 × France
8 × USA
Collaborated with:
D.Blaauw V.Zolotov T.Edwards A.Dharchoudhury S.Sundareswaran M.Zhao Y.Fu M.R.Becer P.Ghanta S.B.K.Vrudhula F.N.Najm C.Oh R.Chaudhry I.N.Hajj A.Das S.Yan S.Bhardwaj J.M.Wang S.Pullela G.Vija S.Pant J.Norton A.Glebov S.Gavrilov K.Gala B.Young J.Wang S.S.Sapatnekar R.Vaidyanathan B.Tutuianu D.Bearden I.Algor S.Sirichotiyakul J.Zuo B.Reschke T.Mewett S.Chandrasekaran
Talks about:
analysi (9) power (9) nois (5) stochast (3) circuit (3) size (3) grid (3) chip (3) distribut (2) crosstalk (2)

Person: Rajendran Panda

DBLP DBLP: Panda:Rajendran

Contributed to:

DAC 20072007
DAC 20062006
DATE 20052005
DAC 20042004
DATE v2 20042004
DAC 20032003
DATE 20022002
DAC 20002000
DAC 19991999
DAC 19981998
DATE 19981998
DAC 19971997

Wrote 18 papers:

On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise (MZ, RP, BR, YF, TM, SC, SS, SY), pp. 162–167.
DAC-2006-GhantaVBP #analysis #correlation #power management #probability #scalability
Stochastic variational analysis of large power grids considering intra-die correlations (PG, SBKV, SB, RP), pp. 211–216.
DAC-2006-ZhaoPSYF #algorithm #linear #megamodelling #performance #programming #using
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming (MZ, RP, SS, SY, YF), pp. 217–222.
DATE-2005-GhantaVPW #analysis #grid #power management #probability #process
Stochastic Power Grid Analysis Considering Process Variations (PG, SBKV, RP, JMW), pp. 964–969.
DAC-2004-PantBZSP #analysis #approach #grid #power management #probability
A stochastic approach To power grid analysis (SP, DB, VZ, SS, RP), pp. 171–176.
DAC-2004-ZhaoFZSP #power management
Optimal placement of power supply pads and pins (MZ, YF, VZ, SS, RP), pp. 165–170.
DATE-v2-2004-GlebovGZOPB #analysis
False-Noise Analysis for Domino Circuits (AG, SG, VZ, CO, RP, MRB), pp. 784–789.
DAC-2003-BecerBAPOZH #reduction
Post-route gate sizing for crosstalk noise reduction (MRB, DB, IA, RP, CO, VZ, INH), pp. 954–957.
DATE-2002-BecerZBPH #analysis #using
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model (MRB, VZ, DB, RP, INH), pp. 456–463.
DAC-2000-BlaauwPD #graph
Removing user specified false paths from timing graphs (DB, RP, AD), pp. 270–273.
DAC-2000-ChaudhryBPE #analysis
Current signature compression for IR-drop analysis (RC, DB, RP, TE), pp. 162–167.
DAC-2000-GalaZPYWB #analysis #modelling
On-chip inductance modeling and analysis (KG, VZ, RP, BY, JW, DB), pp. 63–68.
DAC-2000-ZhaoPSECB #analysis #network
Hierarchical analysis of power distribution networks (MZ, RP, SSS, TE, RC, DB), pp. 150–155.
DAC-1999-SirichotiyakulEOZDPB #power management
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DAC-1998-DharchoudhuryPBVTB #analysis #design #network
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
DAC-1998-PandaDENB #design #incremental #migration #named
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization (RP, AD, TE, JN, DB), pp. 388–391.
CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
DAC-1997-PandaN #power management #synthesis
Technology-Dependent Transformations for Low-Power Synthesis (RP, FNN), pp. 650–655.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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