Travelled to:1 × Austria
1 × France
1 × Italy
1 × Russia
1 × Singapore
1 × USA
Collaborated with:J.Sun Y.Liu Y.L.0003 J.S.Dong H.Xiao P.Hsiung T.K.Nguyen É.André H.Hansen J.S.0001 B.C.0001 S.Qin Y.Li X.Xie C.Sun J.L.0001 L.L.0044 Q.L.Le D.Sanán M.Chandramohan A.Tiu L.Zou X.Li H.Wang Y.L.0001 T.L.0002
Talks about:composit (3) system (3) learn (3) time (3) loop (3) synthesi (2) interpol (2) abstract (2) concurr (2) automat (2)
Person: Shang-Wei Lin
DBLP: Lin:Shang=Wei
Contributed to:
2015
2014
2014
2013201320122015201720172019Wrote 12 papers:
- ESEC-FSE-2015-SunXLLQ #abstraction #learning #named #testing #validation
- TLV: abstraction through testing, learning, and validation (JS, HX, YL, SWL, SQ), pp. 698–709.
- CAV-2014-HansenLLN0 #abstraction #automaton #partial order #reduction #women
- Diamonds Are a Girl’s Best Friend: Partial Order Reduction for Timed Automata with Abstractions (HH, SWL, YL, TKN, JS), pp. 391–406.
- FM-2014-LinH #composition #concurrent #learning #model checking #synthesis
- Compositional Synthesis of Concurrent Systems through Causal Model Checking and Learning (SWL, PAH), pp. 416–431.
- ASE-2013-Xiao0LLS #learning #named #type system
- TzuYu: Learning stateful typestates (HX, JS, YL, SWL, CS), pp. 432–442.
- CAV-2013-AndreLSDL #concurrent #named #parametricity #realtime #synthesis
- PSyHCoS: Parameter Synthesis for Hierarchical Concurrent Real-Time Systems (ÉA, YL, JS, JSD, SWL), pp. 984–989.
- FM-2012-LinLSDA #automation #composition #verification
- Automatic Compositional Verification of Timed Systems (SWL, YL, JS, JSD, ÉA), pp. 272–276.
- ASE-2015-LinSNLD #composition #verification
- Interpolation Guided Compositional Verification (T) (SWL, JS, TKN, YL, JSD), pp. 65–74.
- ASE-2017-LinSXLSH #invariant #named
- FiB: squeezing loop invariants by interpolation between Forward/Backward predicate transformers (SWL, JS0, HX, YL0, DS, HH), pp. 793–803.
- ASE-2017-LiSLLL #automation #generative #invariant #refinement
- Automatic loop-invariant generation and refinement through selective sampling (JL0, JS0, LL0, QLL, SWL), pp. 782–792.
- ESEC-FSE-2017-LiCCLLT #fuzzing #named
- Steelix: program-state based binary fuzzing (YL, BC0, MC, SWL, YL0, AT), pp. 627–637.
- ESEC-FSE-2017-XieCZLLL #analysis #named #termination
- Loopster: static loop termination analysis (XX, BC0, LZ, SWL, YL0, XL), pp. 84–94.
- ESEC-FSE-2019-WangXLLLQLL #layout #memory management
- Locating vulnerabilities in binaries via memory layout recovering (HW, XX, SWL, YL0, YL, SQ, YL0, TL0), pp. 718–728.