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Travelled to:
1 × USA
Collaborated with:
C.Huang
Talks about:
simultan (1) transit (1) static (1) formal (1) consid (1) analyz (1) input (1) time (1) path (1) fals (1)

Person: Shihheng Tsai

DBLP DBLP: Tsai:Shihheng

Contributed to:

DAC 20092009

Wrote 1 papers:

DAC-2009-TsaiH
A false-path aware formal static timing analyzer considering simultaneous input transitions (ST, CYH), pp. 25–30.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.