Travelled to:2 × France
2 × Germany
2 × USA
Collaborated with:C.Wu S.Tsai K.Cheng C.Lai K.Khoo K.Tang P.Huang C.Chou Y.Yeh H.Lin T.Lin C.Lee
Talks about:circuit (2) multi (2) check (2) sat (2) constraint (1) techniqu (1) synchron (1) structur (1) simultan (1) platform (1)
Person: Chung-Yang Huang
DBLP: Huang:Chung=Yang
Contributed to:
20122011
2009200820072000Wrote 6 papers:
- DATE-2012-TangHCH #generative #logic #multi #reduction
- Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction (KFT, PKH, CNC, CYH), pp. 1567–1572.
- DATE-2011-YehHWL #framework #simulation
- Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method (YFY, CYH, CAW, HCL), pp. 353–358.
- DAC-2009-TsaiH
- A false-path aware formal static timing analyzer considering simultaneous input transitions (ST, CYH), pp. 25–30.
- DATE-2008-LaiHK #identification #multi #verification
- Improving Constant-Coefficient Multiplier Verification by Partial Product Identification (CYL, CYH, KYK), pp. 813–818.
- DATE-2007-WuLLH #named #robust #satisfiability
- QuteSAT: a robust circuit-based SAT solver for complex circuit structure (CAW, THL, CCL, CYH), pp. 1313–1318.
- DAC-2000-HuangC #composition #constraints
- Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques (CYH, KTC), pp. 118–123.