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Travelled to:
1 × France
Collaborated with:
X.Chen S.Li J.Schleifer A.Chattopadhyay G.Ascheid T.G.Noll
Talks about:
synthesi (1) model (1) level (1) fpgas (1) embed (1) high (1)

Person: Thomas Coenen

DBLP DBLP: Coenen:Thomas

Contributed to:

DATE 20132013

Wrote 1 papers:

DATE-2013-ChenLSCCAN #embedded #modelling #synthesis
High-level modeling and synthesis for embedded FPGAs (XC, SL, JS, TC, AC, GA, TGN), pp. 1565–1570.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.