BibSLEIGH — Gerd

Travelled to:

4 × France
4 × USA
7 × Germany

Collaborated with:

R.Leupers H.Meyr K.Karuri A.Chattopadhyay J.Castrillón M.Hohenauer S.Kraemer G.Braun L.G.Murillo J.F.Eusse H.Scharwächter J.Ceng T.Kogel D.Kammler O.Schliebusch J.Jovic S.Yakoushkin X.Chen T.Kempf H.Ishebabi A.Nohl A.Tretter W.Sheng E.M.Witte S.Wawroschek J.H.Weinstock C.Schumacher L.Tosoratto W.Verachtert T.Ashby A.Vandecappelle M.Kedia P.Sudowe B.Leibe T.Sadasue L.Gao S.Wallentowitz M.A.A.Faruque M.Odendahl A.Goens B.Ries B.Vöcking T.Henriksson S.Schürmans D.Zhang D.Auras X.Chen L.Wang S.Li J.Schleifer T.Coenen T.G.Noll F.Engel G.Bette B.Singh W.Ahmed M.Doerper B.Vanthournout A.Wieferink R.Velasquez A.Stulova M.Steinert T.Isshiki H.Kunieda B.Geukes L.Fanucci M.Cassiano S.Saponara O.Wahlen H.v.Someren

Talks about:

processor (9) system (6) design (6) applic (6) architectur (5) simul (5) model (5) level (5) use (5) map (5)

Person: Gerd Ascheid

DBLP: Ascheid:Gerd

Contributed to:

2014

2013

2012

2010

2008

2007

2006

2005

2004

Wrote 28 papers:

DATE-2014-EusseLASLS #architecture #component #embedded #flexibility: A flexible ASIP architecture for connected components labeling in embedded vision applications (JFE, RL, GA, PS, BL, TS), pp. 1–6.
DATE-2014-MurilloWCLA #automation #concurrent #constraints #debugging #detection: Automatic detection of concurrency bugs through event ordering constraints (LGM, SW, JC, RL, GA), pp. 1–6.
DATE-2014-OdendahlGLARVH #manycore: Optimized buffer allocation in multicore platforms (MO, AG, RL, GA, BR, BV, TH), pp. 1–6.
DATE-2014-WeinstockSLAT #parallel #simulation: Time-decoupled parallel SystemC simulation (JHW, CS, RL, GA, LT), pp. 1–4.
DAC-2013-SchurmansZALACW #architecture #automation #communication #modelling #using: Creation of ESL power models for communication architectures using automatic calibration (SS, DZ, DA, RL, GA, XC, LW), p. 58.
DATE-2013-ChenLSCCAN #embedded #modelling #synthesis: High-level modeling and synthesis for embedded FPGAs (XC, SL, JS, TC, AC, GA, TGN), pp. 1565–1570.
DAC-2012-CastrillonTLA: Communication-aware mapping of KPN applications onto heterogeneous MPSoCs (JC, AT, RL, GA), pp. 1266–1271.
DAC-2012-MurilloEJYLA #hybrid #simulation: Synchronization for hybrid MPSoC full-system simulation (LGM, JFE, JJ, SY, RL, GA), pp. 121–126.
DATE-2012-JovicYMELA #hybrid #simulation: Hybrid simulation for extensible processor cores (JJ, SY, LGM, JFE, RL, GA), pp. 288–291.
DATE-2010-CastrillonVSSCLAM #analysis: Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms (JC, RV, AS, WS, JC, RL, GA, HM), pp. 753–758.
DAC-2008-CengCSSLAMIK #framework #named #parallel: MAPS: an integrated framework for MPSoC application parallelization (JC, JC, WS, HS, RL, GA, HM, TI, HK), pp. 754–759.
DAC-2008-GaoKKLAM #estimation #hybrid #multi #performance #simulation #using: Multiprocessor performance estimation using hybrid simulation (LG, KK, SK, RL, GA, HM), pp. 325–330.
DATE-2008-ChattopadhyayCILAM #architecture #configuration management #modelling: High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures (AC, XC, HI, RL, GA, HM), pp. 1334–1339.
DATE-2008-HohenauerELAMBS #execution #optimisation: Retargetable Code Optimization for Predicated Execution (MH, FE, RL, GA, HM, GB, BS), pp. 1492–1497.
DATE-2008-LeupersAVAV #architecture #design #multi: System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures (RL, GA, WV, TA, AV).
DATE-2007-ChattopadhyayAKKLAM #configuration management #design #embedded: Design space exploration of partially re-configurable embedded processors (AC, WA, KK, DK, RL, GA, HM), pp. 319–324.
DATE-2007-KraemerLAM #interactive #parallel #program transformation #source code #using: Interactive presentation: SoftSIMD — exploiting subword parallelism using source code transformations (SK, RL, GA, HM), pp. 1349–1354.
DATE-2006-ChattopadhyayGKWSILAM #automation #embedded: Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
DATE-2006-KempfKWALM #estimation #fine-grained #framework #performance #using: A SW performance estimation framework for early system-level-design using fine-grained instrumentation (TK, KK, SW, GA, RL, HM), pp. 468–473.
DATE-2006-ScharwachterHLAM #hardware #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-DF-2006-FanucciCSKWSALM #design #image #linear #synthesis: ASIP design and synthesis for non linear filtering in image processing (LF, MC, SS, DK, EMW, OS, GA, RL, HM), pp. 233–238.
DATE-DF-2006-KaruriLAMK #composition #design #float #implementation: Design and implementation of a modular and portable IEEE 754 compliant floating-point unit (KK, RL, GA, HM, MK), pp. 221–226.
DAC-2005-KaruriFKLAM #design #fine-grained #profiling #source code: Fine-grained application source code profiling for ASIP design (KK, MAAF, SK, RL, GA, HM), pp. 329–334.
DATE-2005-CengHLAMB #c #compilation #modelling #semantics: C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
DATE-2005-KempfDLAMKV #composition #framework #multi #simulation: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (TK, MD, RL, GA, HM, TK, BV), pp. 876–881.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v2-2004-HohenauerSKWKLAMBS #c #compilation #generative #modelling: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (MH, HS, KK, OW, TK, RL, GA, HM, GB, HvS), pp. 1276–1283.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.