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Travelled to:
3 × France
Collaborated with:
M.Wolf C.Paulus R.Thewes
Talks about:
analog (3) generat (2) optim (2) modul (2) constraint (1) independ (1) topolog (1) circuit (1) automat (1) layout (1)

Person: Ulrich Kleine

DBLP DBLP: Kleine:Ulrich

Contributed to:

DATE 20002000
DATE 19981998
ED&TC 19971997

Wrote 3 papers:

DATE-2000-PaulusKT #constraints #optimisation
Area Optimization of Analog Circuits Considering Matching Constraints (CP, UK, RT), p. 738.
DATE-1998-WolfK #automation #generative #optimisation
Automatic Topology Optimization for Analog Module Generators (MW, UK), pp. 961–962.
EDTC-1997-WolfK #generative #independence
Application independent module generation in analog layouts (MW, UK), p. 624.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.