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Travelled to:
2 × USA
Collaborated with:
R.A.Rohrer J.E.Bracken
Talks about:
interconnect (2) nonlinear (1) problem (1) general (1) analysi (1) effici (1) driver (1) spice (1) simul (1) model (1)

Person: Vivek Raghavan

DBLP DBLP: Raghavan:Vivek

Contributed to:

DAC 19921992
DAC 19911991

Wrote 2 papers:

DAC-1992-RaghavanBR #named #performance #problem #simulation
AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect Problems (VR, JEB, RAR), pp. 87–92.
DAC-1991-RaghavanR #analysis
A New Nonlinear Driver Model for Interconnect Analysis (VR, RAR), pp. 561–566.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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