Proceedings of the 28th Design Automation Conference
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A. Richard Newton
Proceedings of the 28th Design Automation Conference
DAC, 1991.

SYS
DBLP
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@proceedings{DAC-1991,
	acmid         = "127601",
	address       = "San Francisco, California, USA",
	editor        = "A. Richard Newton",
	isbn          = "0-89791395-7",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 28th Design Automation Conference}",
	year          = 1991,
}

Contents (139 items)

DAC-1991-GebotysE #architecture #scheduling #synthesis
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis (CHG, MIE), pp. 2–7.
DAC-1991-PrakashP #architecture #multi #synthesis
Synthesis of Application-Specific Multiprocessor Architectures (SP, ACP), pp. 8–13.
DAC-1991-Hafer #constraints #hardware #synthesis
Constraint improvements for MILP-based hardware synthesis (LJH), pp. 14–19.
DAC-1991-ShihK #approach #equation #named #performance #using
ILLIADS: A New Fast MOS Timing Simulator Using Direct Equation-Solving Approach (YHS, SMK), pp. 20–25.
DAC-1991-SteinNGR #adaptation #named #simulation
ADAPTS: A Digital Transient Simulation Strategy for Integrated Circuits (ADS, TVN, BJG, RAR), pp. 26–31.
DAC-1991-VisweswariahR #performance #simulation
Efficient Simulation of Bipolar Digital ICs (CV, RAR), pp. 32–37.
DAC-1991-DaiDS #generative #sketching
Topological Routing in SURF: Generating a Rubber-Band sketch (WWMD, TD, DS), pp. 39–44.
DAC-1991-DaiKS #sketching
Routability of a Rubber-Band Sketch (WWMD, RK, MS), pp. 45–48.
DAC-1991-Wang #layout #novel
Novel Routing Schemes for IC Layout, Part I: Two-Layer Channel Routing (DCW), pp. 49–53.
DAC-1991-RaithB
A New Hypergraph Based Rip-Up and Reroute Strategy (MR, MB), pp. 54–59.
DAC-1991-FangCFC #multi #problem
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems (SCF, KEC, WSF, SJC), pp. 60–65.
DAC-1991-Krasniewski #logic #performance #pseudo #synthesis #testing
Logic Synthesis for Efficient Pseudoexhaustive Testability (AK), pp. 66–72.
DAC-1991-MaoC #design #fault
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage (WM, MDC), pp. 73–79.
DAC-1991-ChengDK #design #generative #robust #standard #synthesis #testing
Robust Delay-Fault Test Generation and Synthesis for Testability Under A Standard Scan Design Methodology (KTC, SD, KK), pp. 80–86.
DAC-1991-WilliamsUM #network #testing
The Interdependence Between Delay-Optimization of Synthesized Networks and Testing (TWW, BU, MRM), pp. 87–92.
DAC-1991-CrastesSS
A Technology Mapping Method Based On Perfect And Semi-Perfect Matchings (MC, KS, GS), pp. 93–98.
DAC-1991-PedramB #layout
Layout Driven Technology Mapping (MP, NBB), pp. 99–105.
DAC-1991-MorganG #logic #synthesis
An ECL Logic Synthesis System (VM, DG), pp. 106–111.
DAC-1991-YoshikawaITSNK #optimisation
Timing Optimization on Mapped Circuits (KY, HI, HT, SS, NN, AK), pp. 112–117.
DAC-1991-Kazyonnov #automation #design
Design Automation in the Soviet Union: History and Status (GGK), p. 118.
DAC-1991-LinPHL #reduction
Channel Density Reduction by Routing Over The Cells (MSL, HWP, CYH, YLL), pp. 120–125.
DAC-1991-HolmesSS #algorithm #using
New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals (NDH, NAS, MS), pp. 126–131.
DAC-1991-EnbodyLT #3d
Routing the 3-D Chip (RJE, GL, KHT), pp. 132–137.
DAC-1991-VandrisS #algorithm #fault #memory management #performance #simulation
Algorithms for Fast, Memory Efficient Switch-Level Fault Simulation (EV, GES), pp. 138–143.
DAC-1991-PitchumaniMR #fault #simulation
A System for Fault Diagnosis and Simulation of VHDL Descriptions (VP, PM, NR), pp. 144–150.
DAC-1991-Kitamura #algorithm #fault #simulation
Sequential Circuit Fault Simulation by Fault Information Tracing Algorithm: FIT (YK), pp. 151–154.
DAC-1991-PatilBP #generative #parallel #testing
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors (SP, PB, JHP), pp. 155–159.
DAC-1991-MontessoroG #concurrent #fault #multi #named #performance #simulation
Creator: General and Efficient Multilevel Concurrent Fault Simulation (PLM, SG), pp. 160–163.
DAC-1991-Cheng #on the
On Removing Redundancy in Sequential Circuits (KTC), pp. 164–169.
DAC-1991-SaldanhaVBS #constraints #encoding #framework
A Framework for Satisfying Input and Output Encoding Constraints (AS, TV, RKB, ALSV), pp. 170–175.
DAC-1991-CiesielskiSD #approach #automaton #encoding
A Unified Approach to Input-Output Encoding for FSM State Assignment (MJC, JJS, MD), pp. 176–181.
DAC-1991-GeigerM #algebra #automaton #benchmark #composition #metric
FSM Decomposition Revisited: Algebraic Structure Theory Applied to MCNC Benchmark FSMs (MG, TMW), pp. 182–185.
DAC-1991-Hill #array #design #programmable
A CAD System for the Design of Field Programmable Gate Arrays (DDH), pp. 187–192.
DAC-1991-TeraiGWKEHH #automation #concept #design
Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers (HT, FG, KW, TK, ME, SH, MH), pp. 193–198.
DAC-1991-YountS #design #named #reliability
SIDECAR: Design Support for Reliability (CRY, DPS), pp. 199–204.
DAC-1991-AuWS #automation #generative #simulation
Automatic Generation of Compiled Simulations through Program Specialization (WYA, DW, SS), pp. 205–210.
DAC-1991-Jones91a #simulation
Accelerating Switch-Level Simulation by Function Caching (LGJ), pp. 211–214.
DAC-1991-ChewS #logic #multi #simulation
Utilizing Logic Information in Multi-Level Timing Simulation (MPC, AJS), pp. 215–218.
DAC-1991-JainB #hardware #simulation
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators (AJ, REB), pp. 219–222.
DAC-1991-BrinerEK #parallel #simulation
Breaking the Barrier of Parallel Simulation of Digital Systems (JVBJ, JLE, GK), pp. 223–226.
DAC-1991-FrancisRV #named #performance
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs (RJF, JR, ZGV), pp. 227–233.
DAC-1991-ErcolaniM #array #programmable
Technology Mapping for Electrically Programmable Gate Arrays (SE, GDM), pp. 234–239.
DAC-1991-Karplus #array #named #programmable
Xmap: A Technology Mapper for Table-Lookup Field-Programmable Gate Arrays (KK), pp. 240–243.
DAC-1991-Karplus91a #array #named #programmable
Amap: A Technology Mapper for Selector-Based Field-Programmable Gate Arrays (KK), pp. 244–247.
DAC-1991-Woo #heuristic
A Heuristic Method for FPGA Technology Mapping Based on the Edge Visibility (NSW), pp. 248–251.
DAC-1991-OgawaIMIST #constraints #design
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design (YO, TI, YM, TI, YS, RT), pp. 253–258.
DAC-1991-MassonEBWC #implementation #lisp #object-oriented
Object Oriented Lisp Implementation of the CHEOPS VLSI Floor Planning and Routing System (CM, RE, DB, DW, GC), pp. 259–264.
DAC-1991-Kozminski #benchmark #evolution #layout #metric #synthesis
Benchmarks for Layout Synthesis — Evolution and Current Status (KK), pp. 265–270.
DAC-1991-ChiuP #design #synthesis #testing
A Design for Testability Scheme with Applications to Data Path Synthesis (SC, CAP), pp. 271–277.
DAC-1991-ChakrabortyBBL #testing #using
Enhanced Controllability for IDDQ Test Sets Using Partial Scan (TJC, SB, RB, CJL), pp. 278–281.
DAC-1991-ChandraFGP #novel
ATPG Based on a Novel Grid-Addressable Latch Element (SJC, TF, TG, KP), pp. 282–286.
DAC-1991-Chen #clustering #concurrent #graph #scheduling
Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit (CIHC), pp. 287–290.
DAC-1991-WuR #effectiveness #evaluation
Delay Test Effectiveness Evaluation of LSSD-Based VLSI Vogic Circuits (DMW, CER), pp. 291–295.
DAC-1991-LinL #automation #synthesis
Automatic Synthesis of Asynchronous Circuits (KJL, CSL), pp. 296–301.
DAC-1991-LavagnoKS #algorithm #synthesis
Algorithms for Synthesis of Hazard-Free Asynchronous Circuits (LL, KK, ALSV), pp. 302–308.
DAC-1991-LaddB #finite #multi #state machine #synthesis
Synthesis of Multiple-Input Change Asynchronous Finite state Machines (ML, WPB), pp. 309–314.
DAC-1991-CardenC #algorithm #approximate #multi #performance #using
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm (RCCI, CKC), pp. 316–321.
DAC-1991-KahngCR #geometry #recursion
High-Performance Clock Routing Based on Recursive Geometric Aatching (ABK, JC, GR), pp. 322–327.
DAC-1991-CaiW #on the
On Minimizing the Number of L-Shaped Channels (YC, DFW), pp. 328–334.
DAC-1991-GuruswamyW #multi
A General Multi-Layer Area Router (MG, DFW), pp. 335–340.
DAC-1991-PomeranzR #fault #on the #using
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model (IP, SMR), pp. 341–346.
DAC-1991-PaterasR #correlation #generative #multi #random #testing
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits (SP, JR), pp. 347–352.
DAC-1991-ChakradharA #algorithm #generative #testing #transitive
A Transitive Closure Based Algorithm for Test Generation (STC, VDA), pp. 353–358.
DAC-1991-DevadasKM #algorithm #generative #multi #testing
A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults (SD, KK, SM), pp. 359–365.
DAC-1991-KuFM #optimisation
Control Optimization Based on Resynchronization of Operations (DCK, DF, GDM), pp. 366–371.
DAC-1991-EschermannW #approach #finite #self #state machine #synthesis
A Unified Approach for the Synthesis of Self-Testable Finite State Machines (BE, HJW), pp. 372–377.
DAC-1991-PapachristouCH #design #self #synthesis
A Data Path Synthesis Method for Self-Testable Designs (CAP, SC, HH), pp. 378–384.
DAC-1991-RaghavendraL #automation #self #synthesis
Automated Micro-Roll-back Self-Recovery Synthesis (VR, CL), pp. 385–390.
DAC-1991-BuschV #design #hardware
Proof-Aided Design of Verified Hardware (HB, GV), pp. 391–396.
DAC-1991-BryantBS #evaluation #hardware #verification
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation (REB, DLB, CJHS), pp. 397–402.
DAC-1991-BurchCL #model checking #representation
Representing Circuits More Efficiently in Symbolic Model Checking (JRB, EMC, DEL), pp. 403–407.
DAC-1991-Burch #multi #using #verification
Using BDDs to Verify Multipliers (JRB), pp. 408–412.
DAC-1991-OchiIY
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing (HO, NI, SY), pp. 413–416.
DAC-1991-ButlerRKM #diagrams #heuristic #order #performance
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams (KMB, DER, RK, MRM), pp. 417–420.
DAC-1991-YehCL #algorithm #clustering #multi
A General Purpose Multiple Way Partitioning Algorithm (CWY, CKC, TTYL), pp. 421–426.
DAC-1991-SiglDJ #linear #polynomial #question
Analytical Placement: A Linear or a Quadratic Objective Function? (GS, KD, FMJ), pp. 427–432.
DAC-1991-OnoderaTT #bound #layout
Branch-and-Bound Placement for Building Block Layout (HO, YT, KT), pp. 433–439.
DAC-1991-WuL #fault #probability #testing
A Probabilistic Testability Measure for Delay Faults (WCW, CLL), pp. 440–445.
DAC-1991-BeerelM #testing
Testability of Asynchronous Timed Control Circuits with Delay Assumptions (PAB, THYM), pp. 446–451.
DAC-1991-SastryM #analysis #branch #process
A Branching Process Model for Observability Analysis of Combinational Circuits (SS, AM), pp. 452–457.
DAC-1991-ChenMMF #approach #network #optimisation
A Resynthesis Approach for Network Optimization (KCC, YM, SM, MF), pp. 458–463.
DAC-1991-LimquecoM #logic #network #optimisation
Logic Optimization of MOS Networks (JCL, SM), pp. 464–469.
DAC-1991-SoeK #logic #using
Logic Minimization using Two-column Rectangle Replacement (SS, KK), pp. 470–473.
DAC-1991-HoS #flexibility #matrix
Flexible Transistor Matrix (FTM) (KCH, SS), pp. 475–480.
DAC-1991-HwangHLH #automation #generative #layout #performance
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation (CYH, YCH, YLL, YCH), pp. 481–486.
DAC-1991-MaziaszH
Exact Width and Height Minimization of CMOS Cells (RLM, JPH), pp. 487–493.
DAC-1991-HussG #testing
Optimal Ordering of Analog Integrated Circuit Tests to Minimize Test Time (SDH, RSG), pp. 494–499.
DAC-1991-Gad-El-KarimG #generative #layout #performance
Generation of Performance Sensitivities for Analog Cell Layout (GGEK, RSG), pp. 500–505.
DAC-1991-DonzelleDHPS #approach #automation #constraints #design
A Constraint Based Approach to Automatic Design of Analog Cells (LOD, PFD, BH, JP, PS), pp. 506–509.
DAC-1991-MogakiKSY #constraints #layout
A Layout Improvement Method Based on Constraint Propagation for Analog LSI’s (MM, NK, NS, YY), pp. 510–513.
DAC-1991-KucukcakarP #constraints #named
CHOP: A Constraint-Driven System-Level Partitioner (KK, ACP), pp. 514–519.
DAC-1991-Fuhrman #industrial #synthesis #tool support
Industrial Extensions to University High Level Synthesis Tools: Making It Work in the Real World (TEF), pp. 520–525.
DAC-1991-DuttK #library #synthesis
Bridging High-Level Synthesis to RTL Technology Libraries (NDD, JRK), pp. 526–529.
DAC-1991-ParkerGH #design #physics #trade-off
The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve (ACP, PG, AH), pp. 530–534.
DAC-1991-LiuDC #algorithm #parallel #performance
An Efficient Parallel Critical Path Algorithm (LRL, DHCD, HCC), pp. 535–540.
DAC-1991-JuS #identification #incremental
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths (YCJ, RAS), pp. 541–546.
DAC-1991-ChenDL #optimisation #performance
Critical Path Selection for Performance Optimization (HCC, DHCD, LRL), pp. 547–550.
DAC-1991-PanBGGY #design #verification
Timing Verification on a 1.2M-Device Full-Custom CMOS Design (JP, LLB, JG, WJG, YTY), pp. 551–554.
DAC-1991-RatzlaffGP #agile #named
RICE: Rapid Interconnect Circuit Evaluator (CLR, NG, LTP), pp. 555–560.
DAC-1991-RaghavanR #analysis
A New Nonlinear Driver Model for Interconnect Analysis (VR, RAR), pp. 561–566.
DAC-1991-MattesWBD
Propagation Delay Calculation for Interconnection Nets on Printed Circuit Boards by Reflected Waves (HM, WW, GB, RD), pp. 567–572.
DAC-1991-ChinDBWND
Linking TCAD to EDA — Benefits and Issues (GRC, WCDJ, DSB, ASW, ARN, RWD), pp. 573–578.
DAC-1991-WalkerKS #database #editing #process #representation #statistics
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator (DMHW, CSK, AJS), pp. 579–584.
DAC-1991-WuYYL #design #multi #named #optimisation #process
GOALSERVER: A Multiobjective Design Optimization Tool for IC Fabrication Process (LW, ZY, ZY, ZL), pp. 585–590.
DAC-1991-BergamaschiCP #analysis #synthesis #using
Data-Path Synthesis Using Path Analysis (RAB, RC, MP), pp. 591–596.
DAC-1991-NoteGCM #architecture #named #synthesis #throughput
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications (SN, WG, FC, HDM), pp. 597–602.
DAC-1991-ChenM #pipes and filters #scheduling
Datapath Scheduling for Two-Level Pipelining (CYRC, MZM), pp. 603–606.
DAC-1991-PangrleBLS #synthesis
Relevant Issues in High-Level Connectivity Synthesis (BMP, FB, DAL, AS), pp. 607–610.
DAC-1991-BenkoskiS #layout #synthesis #verification
The Role of Timing Verification in Layout Synthesis (JB, AJS), pp. 612–619.
DAC-1991-TsayK #approach #optimisation #performance
An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement (RST, JK), pp. 620–625.
DAC-1991-Luk #constraints #generative #layout #performance #physics
A Fast Physical Constraint Generator for Timing Driven Layout (WKL), pp. 626–631.
DAC-1991-SutanthavibulS #predict
Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement (SS, ES), pp. 632–635.
DAC-1991-Srinivasan #algorithm
An Algorithm for Performance-Driven Initial Placement of Small-Cell ICs (AS), pp. 636–639.
DAC-1991-JoyC #multi
Placement for Clock Period Minimization With Multiple Wave Propagation (DAJ, MJC), pp. 640–643.
DAC-1991-Najm #probability #process
Transition Density, A Stochastic Measure of Activity in Digital Circuits (FNN), pp. 644–649.
DAC-1991-DeguchiIY #analysis #fault #logic #probability
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits (YD, NI, SY), pp. 650–655.
DAC-1991-AmonB #behaviour #named
OEsim: A Simulator for Timing Behavior (TA, GB), pp. 656–661.
DAC-1991-DoukasL #constraints #named #verification
CLOVER: A Timing Constraints Verification System (DD, ASL), pp. 662–667.
DAC-1991-WengP #3d #scheduling #synthesis
3D Scheduling: High-Level Synthesis with Floorplanning (JPW, ACP), pp. 668–673.
DAC-1991-LyM #bottom-up #fuzzy #synthesis
Bottom Up Synthesis Based on Fuzzy Schedules (TAL, JTM), pp. 674–679.
DAC-1991-ParkK #automation #performance #scheduling
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis (ICP, CMK), pp. 680–685.
DAC-1991-JainMSW #empirical #evaluation #heuristic #scheduling #synthesis
Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics (RJ, AM, AS, HW), pp. 686–689.
DAC-1991-AmonB91a #case study #synthesis
Sizing Synchronization Queues: A Case Study in Higher Level Synthesis (TA, GB), pp. 690–693.
DAC-1991-AllenRF #framework
The MCC CAD Framework Methodology Management System (WA, DR, KWF), pp. 694–698.
DAC-1991-BanksBEFH #configuration management #data transformation #framework
A Configuration Management System in a Data Management Framework (SB, CB, RE, LF, PH), pp. 699–703.
DAC-1991-WagnerL #design #framework
Design Version Management in the GARDEN Framework (FRW, AHVdL), pp. 704–710.
DAC-1991-BoschBW #design #framework
Design Flow Management in the NELSIS CAD Framework (KOtB, PB, PvdW), pp. 711–716.
DAC-1991-Hwang #analysis #named
REX — A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis (JPH), pp. 717–722.
DAC-1991-Utesch #adaptation #approach #interactive #using
A New Approach to Hierarchical Adaptation Using Sequence-Control Based on Cell Interactions (MCU), pp. 723–726.
DAC-1991-DoodWLS #2d #geometry
A Two-Dimensional Topological Compactor With Octagonal Geometry (PdD, JW, EL, RS), pp. 727–731.
DAC-1991-Harrison #layout #using
VLSI Layout Compaction Using Radix Priority Search Trees (AJH), pp. 732–735.
DAC-1991-DuttL #assembly #constraints #generative #on the
On Minimal Closure Constraint Generation for Symbolic Cell Assembly (DD, CYL), pp. 736–739.
DAC-1991-RoychowdhuryP #performance #simulation
Efficient Transient Simulation of Lossy Interconnect (JSR, DOP), pp. 740–745.
DAC-1991-BarkatullahC
A Transmission Line Simulator for GaAs Integrated Circuits (JSB, SC), pp. 746–751.
DAC-1991-YangCYDH #modelling #parametricity #simulation
Modeling and Simulation of High-Frequency Integrated Circuits Based on Scattering Parameters (ATY, CHC, JTY, RRD, JPH), pp. 752–757.
DAC-1991-HuHB #pipes and filters
Minimizing the Number of Delay Buffers in the Synchronization of Pipelined Systems (XH, RGH, SCB), pp. 758–763.
DAC-1991-HwangHL #functional #pipes and filters #scheduling
Scheduling for Functional Pipelining and Loop Winding (CTH, YCH, YLL), pp. 764–769.
DAC-1991-NicolauP #incremental #reduction #synthesis
Incremental Tree Height Reduction for High Level Synthesis (AN, RP), pp. 770–774.
DAC-1991-LoboP #optimisation #scheduling
Redundant Operator Creation: A Scheduling Optimization Technique (DAL, BMP), pp. 775–778.

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