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Travelled to:
2 × USA
Collaborated with:
M.Marek-Sadowska
Talks about:
integr (2) microprocessor (1) floorplan (1) regular (1) analysi (1) system (1) layout (1) effect (1) level (1) grain (1)

Person: Vivek S. Nandakumar

DBLP DBLP: Nandakumar:Vivek_S=

Contributed to:

DAC 20142014
DAC 20112011

Wrote 2 papers:

DAC-2014-NandakumarM #analysis
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs (VSN, MMS), p. 6.
DAC-2011-NandakumarM #3d #layout
Layout effects in fine grain 3D integrated regular microprocessor blocks (VSN, MMS), pp. 639–644.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.