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Travelled to:
1 × Germany
Collaborated with:
K.J.Kulikowski Z.Wang A.Taubin
Talks about:
mismatch (1) insensit (1) capacit (1) balanc (1) power (1) rout (1) gate (1)

Person: Vyas Venkataraman

DBLP DBLP: Venkataraman:Vyas

Contributed to:

DATE 20082008

Wrote 1 papers:

DATE-2008-KulikowskiVWT
Power Balanced Gates Insensitive to Routing Capacitance Mismatch (KJK, VV, ZW, AT), pp. 1280–1285.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.