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Collaborated with:
D.T.Tang C.K.Wong
Talks about:
hierarchi (1) global (1) design (1) custom (1) wire (1) chip (1)

Person: W. K. Luk

DBLP DBLP: Luk:W=_K=

Contributed to:

DAC 19861986

Wrote 1 papers:

DAC-1986-LukTW #design
Hierarchial global wiring for custom chip design (WKL, DTT, CKW), pp. 481–489.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.