Travelled to:2 × USA
Collaborated with:J.Lee W.K.Luk C.K.Wong Z.Barzilai L.M.Huisman G.M.Silberman L.S.Woo
Talks about:simul (2) transistor (1) increment (1) hierarchi (1) algorithm (1) circuit (1) analysi (1) machin (1) global (1) design (1)
Person: Donald T. Tang
DBLP: Tang:Donald_T=
Contributed to:
199519861983Wrote 3 papers:
- DAC-1995-LeeT #algorithm #analysis #incremental
- An Algorithm for Incremental Timing Analysis (JfL, DTT), pp. 696–701.
- DAC-1986-LukTW #design
- Hierarchial global wiring for custom chip design (WKL, DTT, CKW), pp. 481–489.
- DAC-1983-BarzilaiHSTW #logic #simulation #using
- Simulating pass transistor circuits using logic simulation machines (ZB, LMH, GMS, DTT, LSW), pp. 157–163.