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Travelled to:
1 × USA
Collaborated with:
C.Kuo Y.Chen J.Kuan Y.Cheng
Talks about:
methodolog (1) circuit (1) effici (1) design (1) analog (1) yield (1) sampl (1) carlo (1) trim (1) mont (1)

Person: Wei-Yi Hu

DBLP DBLP: Hu:Wei=Yi

Contributed to:

DAC 20122012

Wrote 1 papers:

DAC-2012-KuoHCKC #design #monte carlo #performance
Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits (CCK, WYH, YHC, JFK, YKC), pp. 1113–1118.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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