Travelled to:2 × USA
Collaborated with:C.Teng E.Rosenbaum S.Kang C.Kuo W.Hu Y.Chen J.Kuan A.Dharchoudhury
Talks about:diagnosi (2) reliabl (2) vlsi (2) chip (2) interconnect (1) electromigr (1) methodolog (1) hierarch (1) thermal (1) complet (1)
Person: Yi-Kan Cheng
DBLP: Cheng:Yi=Kan
Contributed to:
20121996Wrote 3 papers:
- DAC-2012-KuoHCKC #design #monte carlo #performance
- Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits (CCK, WYH, YHC, JFK, YKC), pp. 1113–1118.
- DAC-1996-ChengTDRK #named #reliability
- iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.
- DAC-1996-TengCRK #reliability
- Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects (CCT, YKC, ER, SMK), pp. 752–757.