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Travelled to:
2 × USA
Collaborated with:
N.Ishiura S.Yajima
Talks about:
time (2) probabilist (1) asynchron (1) probabl (1) diagram (1) circuit (1) analysi (1) symbol (1) binari (1) simul (1)

Person: Yutaka Deguchi

DBLP DBLP: Deguchi:Yutaka

Contributed to:

DAC 19911991
DAC 19901990

Wrote 2 papers:

DAC-1991-DeguchiIY #analysis #fault #logic #probability
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits (YD, NI, SY), pp. 650–655.
DAC-1990-IshiuraDY #diagrams #simulation #using
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram (NI, YD, SY), pp. 130–135.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.