Travelled to:1 × Canada
1 × Denmark
1 × Japan
7 × USA
Collaborated with:N.Ishiura K.Hamaguchi H.Hiraishi Y.Kambayashi Y.Deguchi H.Ochi H.Yasuura S.Minato M.Takahashi M.Yoshikawa T.Hayashi K.Tanaka T.Sakai Y.Tsuchida Y.Ooi Y.Ono H.Kano S.Kimura
Talks about:time (8) logic (7) symbol (4) verif (4) model (4) use (4) asynchron (3) regular (3) tempor (3) design (3)
Person: Shuzo Yajima
DBLP: Yajima:Shuzo
Contributed to:
19921991
19911990199019891982
1982
1981
1977Wrote 14 papers:
- CAV-1992-HamaguchiHY #branch #design #logic #using #verification
- Design Verification of a Microprocessor Using Branching Time Regular Temporal Logic (KH, HH, SY), pp. 206–219.
- CAV-1991-HamaguchiHY #branch #logic #model checking #using #verification
- Formal Verification of Speed-Dependent Asynchronous Cicuits Using Symbolic Model Checking of branching Time Regular Temporal Logic (KH, HH, SY), pp. 410–420.
- CAV-1991-HiraishiHOY #logic #model checking #verification
- Vectorized Symbolic Model Checking of Computation Tree Logic for Sequential Machine Verification (HH, KH, HO, SY), pp. 214–224.
- DAC-1991-DeguchiIY #analysis #fault #logic #probability
- Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits (YD, NI, SY), pp. 650–655.
- DAC-1991-OchiIY
- Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing (HO, NI, SY), pp. 413–416.
- CAV-1990-HamaguchiHY #branch #complexity #linear #logic #model checking
- Branching Time Regular Temporal Logic for Model Checking with Linear Time Complexity (KH, HH, SY), pp. 253–262.
- DAC-1990-IshiuraDY #diagrams #simulation #using
- Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram (NI, YD, SY), pp. 130–135.
- DAC-1990-IshiuraYY #behaviour #design #hardware #named #semantics
- NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I (NI, HY, SY), pp. 8–13.
- DAC-1990-MinatoIY #diagrams #performance
- Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation (SiM, NI, SY), pp. 52–57.
- DAC-1989-IshiuraTY #behaviour #logic #simulation #verification
- Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits (NI, MT, SY), pp. 497–502.
- DAC-1982-SakaiTYOOKKY #design #interactive #logic #simulation
- An Interactive Simulation System for structured logic design — ISS (TS, YT, HY, YO, YO, HK, SK, SY), pp. 747–754.
- SIGMOD-1982-KambayashiYY #database #distributed #query #using
- Query Processing for Distributed Databases Using Generalized Semi-Joins (YK, MY, SY), pp. 151–160.
- SIGIR-1981-KambayashiHY #clustering
- Dynamic Clustering Procedures for Bibliographic Data (YK, TH, SY), pp. 90–99.
- VLDB-1977-KambayashiTY #relational
- A Relational Data Language with Simplified Binary Relation Handling Capability (YK, KT, SY), pp. 338–350.