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Travelled to:
3 × USA
Collaborated with:
S.Yajima H.Yasuura Y.Deguchi H.Ochi S.Minato M.Takahashi
Talks about:
time (4) asynchron (2) function (2) behavior (2) manipul (2) languag (2) hardwar (2) diagram (2) circuit (2) boolean (2)

Person: Nagisa Ishiura

DBLP DBLP: Ishiura:Nagisa

Contributed to:

DAC 19911991
DAC 19901990
DAC 19891989

Wrote 7 papers:

DAC-1991-DeguchiIY #analysis #fault #logic #probability
Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits (YD, NI, SY), pp. 650–655.
Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing (HO, NI, SY), pp. 413–416.
DAC-1990-IshiuraDY #diagrams #simulation #using
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram (NI, YD, SY), pp. 130–135.
DAC-1990-IshiuraYY #behaviour #design #hardware #named #semantics
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I (NI, HY, SY), pp. 8–13.
DAC-1990-MinatoIY #diagrams #performance
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation (SiM, NI, SY), pp. 52–57.
DAC-1989-IshiuraTY #behaviour #logic #simulation #verification
Time-Symbolic Simulation for Accurate Timing Verification of Asynchronous Behavior of Logic Circuits (NI, MT, SY), pp. 497–502.
DAC-1989-YasuuraI #design #hardware #semantics #standard
Semantics of a Hardware Design Language for Japanese Standardization (HY, NI), pp. 836–839.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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