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Collaborated with:
A.Vladimirescu D.Weiss M.Katevenis A.Kifir K.Danuwidjaja K.C.Ng N.Jain S.Lass
Talks about:
hardwar (1) emphasi (1) circuit (1) acceler (1) vector (1) simul (1)

Person: Zvika Bronstein

DBLP DBLP: Bronstein:Zvika

Contributed to:

DAC 19871987

Wrote 1 papers:

DAC-1987-VladimirescuWKBKDNJL #hardware #simulation
A Vector Hardware Accelerator with Circuit Simulation Emphasis (AV, DW, MK, ZB, AK, KD, KCN, NJ, SL), pp. 89–94.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.