BibSLEIGH corpus
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Travelled to:
1 × Germany
Collaborated with:
A.Makosiej O.Thomas A.Amara D.Weiss M.Katevenis Z.Bronstein A.Kifir K.Danuwidjaja K.C.Ng N.Jain S.Lass
Talks about:
hardwar (1) emphasi (1) circuit (1) acceler (1) vector (1) stabil (1) orient (1) design (1) yield (1) ultra (1)

Person: Andrei Vladimirescu

DBLP DBLP: Vladimirescu:Andrei

Contributed to:

DATE 20122012
DAC 19871987

Wrote 2 papers:

DATE-2012-MakosiejTVA #design #embedded #optimisation #power management
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization (AM, OT, AV, AA), pp. 93–98.
DAC-1987-VladimirescuWKBKDNJL #hardware #simulation
A Vector Hardware Accelerator with Circuit Simulation Emphasis (AV, DW, MK, ZB, AK, KD, KCN, NJ, SL), pp. 89–94.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.