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Used together with:
delay (9)
model (5)
tree (4)
optim (3)
wire (3)

Stem elmor$ (all stems)

10 papers:

DATEDATE-2007-NiM #self
Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DACDAC-2006-ZhouM #energy #estimation
Elmore model for energy estimation in RC trees (QZ, KM), pp. 965–970.
DACDAC-2001-McDonaldB #analysis #simulation #using
Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis (CBM, REB), pp. 283–288.
Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
DACDAC-1998-NassifDH #modelling #robust #verification
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.
Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.
DACDAC-1995-GuptaKTWP #bound
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.
Rectilinear Steiner Trees with Minimum Elmore Delay (KDB, ABK, BAM, GR), pp. 381–386.
DACDAC-1994-Sapatnekar #optimisation
RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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