10 papers:
DATE-2007-NiM #self- Self-heating-aware optimal wire sizing under Elmore delay model (MN, SOM), pp. 1373–1378.
DAC-2006-ZhouM #energy #estimation- Elmore model for energy estimation in RC trees (QZ, KM), pp. 965–970.
- DAC-2001-McDonaldB #analysis #simulation #using
- Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis (CBM, REB), pp. 283–288.
- DAC-1999-IsmailFN
- Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
- DAC-1998-NassifDH #modelling #robust #verification
- Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
- EDTC-1997-Fishburn
- Shaping a VLSI wire to minimize Elmore delay (JPF), pp. 244–251.
- DAC-1996-ChenCW96a
- Optimal Wire-Sizing Formular Under the Elmore Delay Model (CPC, YPC, DFW), pp. 487–490.
- DAC-1995-GuptaKTWP #bound
- The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.
- DAC-1994-BoeseKMR
- Rectilinear Steiner Trees with Minimum Elmore Delay (KDB, ABK, BAM, GR), pp. 381–386.
- DAC-1994-Sapatnekar #optimisation
- RC Interconnect Optimization Under the Elmore Delay Model (SSS), pp. 387–391.
