BibSLEIGH — Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor

Nevine Nassif, Madhav P. Desai, Dale H. Hall
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor
DAC, 1998.

DAC 1998

@inproceedings{DAC-1998-NassifDH,
	author        = "Nevine Nassif and Madhav P. Desai and Dale H. Hall",
	booktitle     = "{Proceedings of the 35th Design Automation Conference}",
	doi           = "10.1145/277044.277104",
	isbn          = "0-89791-964-5",
	pages         = "230--235",
	publisher     = "{ACM Press}",
	title         = "{Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor}",
	year          = 1998,
}

Nevine Nassif, Madhav P. Desai, Dale H. HallRobust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS MicroprocessorDAC, 1998.

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Nevine Nassif, Madhav P. Desai, Dale H. Hall
Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor
DAC, 1998.