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Used together with:
verif (5)
program (4)
processor (3)
time (3)
softwar (2)

Stem esterel$ (all stems)

17 papers:

DACDAC-2010-JuHRC #analysis #multi #source code
Timing analysis of esterel programs on general-purpose multiprocessors (LJ, BKH, AR, SC), pp. 48–51.
DACDAC-2009-JuHCR #analysis #source code
Context-sensitive timing analysis of Esterel programs (LJ, BKH, SC, AR), pp. 870–873.
DATEDATE-2009-MendlerHT #algebra #interface
WCRT algebra and interfaces for esterel-style synchronous processing (MM, RvH, CT), pp. 93–98.
LCTESLCTES-2009-AndreM #requirements #specification #verification
Specification and verification of time requirements with CCSL and Esterel (CA, FM), pp. 167–176.
SACSAC-2006-LiH #concurrent #multi #thread
A concurrent reactive Esterel processor based on multi-threading (XL, RvH), pp. 912–917.
ASPLOSASPLOS-2006-LiBH #concurrent #embedded #multi #thread
Mapping esterel onto a multi-threaded embedded processor (XL, MB, RvH), pp. 303–314.
LCTESLCTES-2006-ProchnowTH #state machine
Synthesizing safe state machines from Esterel (SP, CT, RvH), pp. 113–124.
FASEFASE-2005-Berry #design #industrial #performance #specification
Esterel v7: From Verified Formal Specification to Efficient Industrial Designs (GB), p. 1.
SASSAS-2003-TardieuS #termination
Instantaneous Termination in Pure Esterel (OT, RdS), pp. 91–108.
DACDAC-2000-Edwards #compilation
Compiling Esterel into sequential code (SAE), pp. 322–327.
FMFM-v2-1999-HainquePBN #compilation #composition #named #tool support
Cronos: A Separate Compilation Toolset for Modular Esterel Applications (OH, LP, YLB, EN), pp. 1836–1853.
FMFM-v2-1999-SeshiaSBD
A Translation of Statecharts to Esterel (SAS, RKS, AKB, SDD), pp. 983–1007.
CAVCAV-1999-RameshB #case study #design #pipes and filters #tool support #using #validation
Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study (SR, PB), pp. 84–95.
CAVCAV-1998-Bouali #verification
XEVE, an ESTEREL Verification Environment (AB), pp. 500–504.
TACASTACAS-1997-Berry #hardware #optimisation #source code #synthesis #verification
Hardware and Software Synthesis, Optimization, and Verification from Esterel Programs (GB), pp. 1–3.
CAVCAV-1995-JagadeesanPO #safety #source code #verification
Safety Property Verification of ESTEREL Programs and Applications to Telecommunications Software (LJJ, CP, JVO), pp. 127–140.
CAVCAV-1994-SimoneR #composition #reduction #semantics #verification
Compositional Semantics of ESTEREL and Verification by Compositional Reductions (RdS, AR), pp. 441–454.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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