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Used together with:
system (5)
railway (4)
model (4)
control (3)
formal (2)

Stem interlock$ (all stems)

10 papers:

HCIHIMI-LCCB-2013-KamoT #collaboration #multi
Interlocked Surfaces: A Dynamic Multi-device Collaboration System (HK, JT), pp. 317–325.
ISSTAISSTA-2013-Bonacchi #case study #proving #safety
Formal safety proof: a real case study in a railway interlocking system (AB0), pp. 378–381.
FMFM-2011-HaxthausenKB #automation #development #modelling #verification
Formal Development of a Tool for Automated Modelling and Verification of Relay Interlocking Systems (AEH, AAK, MLB), pp. 118–132.
ECMFAECMDA-FA-2008-ChevillatCSSW #generative #modelling
Model-Based Generation of Interlocking Controller Software from Control Tables (CC, DAC, PAS, JGS, LW), pp. 349–360.
FATESFATES-2005-BlomIPRS #testing
Simulated Time for Testing Railway Interlockings with TTCN-3 (SB, NI, JvdP, AR, NS), pp. 1–15.
DACDAC-2002-EderB #logic #performance #pipes and filters #verification
Achieving maximum performance: a method for the verification of interlocked pipeline control logic (KE, GB), pp. 135–140.
FMFM-v2-1999-ButhS #architecture #communication #design #model checking
Model-Checking the Architectural Design of a Fail-Safe Communication System for Railway Interlocking Systems (BB, MS), p. 1869.
HPCAHPCA-1995-Weiss #implementation #multi #queue
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors (SW), pp. 14–21.
FMFME-1994-Hansen #validation
Validation of a Railway Interlocking Model (KMH), pp. 582–601.
SOSPSOSP-1971-Easton #process
Process Synchronization without Long-Term Interlock (WBE), pp. 95–100.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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