22 papers:
DAC-2015-TashjianD #identification #on the #using- On using control signals for word-level identification in a gate-level netlist (ET, AD), p. 6.
DATE-2015-OyaSYT #classification #identification- A score-based classification method for identifying hardware-trojans at gate-level netlists (MO, YS, MY, NT), pp. 465–470.
SAT-2014-HeymanSMLA #using- Dominant Controllability Check Using QBF-Solver and Netlist Optimizer (TH, DS, YM, LL, HAH), pp. 227–242.
- DATE-2013-LyrasRPS #multi #scalability #simulation
- Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems (GL, DR, AP, DS), pp. 655–658.
- DAC-2010-JindalAHLNW #detection #logic
- Detecting tangled logic structures in VLSI netlists (TJ, CJA, JH, ZL, GJN, CBW), pp. 603–608.
- DAC-2008-EguroH #pipes and filters
- Enhancing timing-driven FPGA placement for pipelined netlists (KE, SH), pp. 34–37.
- DAC-2008-Hurst #automation #logic #synthesis
- Automatic synthesis of clock gating logic with controlled netlist perturbation (APH), pp. 654–657.
ICFP-2008-ParkKI #functional- Functional netlists (SP, JK, HI), pp. 353–366.
CAV-2008-Bjesse #approach #industrial #model checking #word- A Practical Approach to Word Level Model Checking of Industrial Netlists (PB), pp. 446–458.
- DAC-2007-ZhouTLW #how #logic
- How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs (CLZ, WCT, WHL, YLW), pp. 922–927.
- DATE-DF-2004-DaglioIRRS #component #performance #simulation
- Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.
- DATE-1999-KrupnovaS #clustering #multi
- Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs (HK, GS), p. 587–?.
- CAV-1999-BaumgartnerHSA #abstraction #algorithm #model checking
- Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists (JB, TH, VS, AA), pp. 72–83.
- DAC-1994-KuznarBZ #clustering #multi
- Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect (RK, FB, BZ), pp. 238–243.
- DAC-1993-AlpertK #clustering #geometry #multi #performance
- Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning (CJA, ABK), pp. 743–748.
- DAC-1992-BatraC #comparison #named
- Hcompare: A Hierarchical Netlist Comparison Program (PB, DC), pp. 299–304.
- DAC-1992-Peltz #design #interpreter
- An Interpreter for General Netlist Design Rule Checking (GP), pp. 305–310.
- DAC-1992-ZeinED #logic #named
- HLSIM — A New Hierarchical Logic Simulator and Netlist Converter (DAZ, OPE, GSD), pp. 432–437.
- DAC-1989-ChenC #automation #layout
- The Layout Synthesizer: An Automatic Netlist-to-Layout System (CCC, SLC), pp. 232–238.
- DAC-1989-Jones #compilation #online #performance
- Fast Online/Offline Netlist Compilation of Hierarchical Schematics (LGJ), pp. 822–825.
SLP-1987-Reintjes87 #named- AUNT: A Universal Netlist Translator (PBR), pp. 508–515.
- DAC-1985-TygarE #comparison #performance #using
- Efficient netlist comparison using hierarchy and randomization (JDT, RE), pp. 702–708.
