7 papers:
DATE-2009-BombieriFPV #generative- Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.
DAC-2008-Larson- Translation of an existing VMM-based SystemVerilog testbench to OVM (KDL), p. 237.
- DATE-2007-MavroidisP #hardware #performance #synthesis
- Efficient testbench code synthesis for a hardware emulator system (IM, IP), pp. 888–893.
- DATE-2006-BombieriFP #evaluation #on the #reuse #verification
- On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.
- DATE-2006-MatulaM #algorithm #float #formal method #generative #performance #standard #traversal #verification
- A formal model and efficient traversal algorithm for generating testbenches for verification of IEEE standard floating point division (DWM, LDM), pp. 1134–1138.
- DAC-2003-HenftlingZBZE #architecture
- Re-use-centric architecture for a fully accelerated testbench environment (RH, AZ, MB, MZ, WE), pp. 372–375.
- DATE-2003-HenftlingZBEZ #generative
- Platform-Based Testbench Generation (RH, AZ, MB, WE, MZ), pp. 11038–11045.
